DRAM Address Error Detection to Cancel Erroneous Writes
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Solution Overview
Problem
Modern memory systems face significant challenges in error detection and correction, particularly as data transfer rates increase, leading to issues with signal quality due to noise and other factors, where address errors can be more detrimental than data errors, potentially corrupting stored data.
Innovation Solution
A mechanism is implemented in memory systems where the DRAM computes an error-detection code (EDC) based on both address and data, which is then verified by the memory controller. This allows for the detection and prevention of erroneous write operations by canceling them if errors are detected, ensuring error-resistant transmission of both address and data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer rate is increased to improve productivity, then data transmission speed is improved, but signal quality deteriorates due to noise and transmission errors
Solution Approach 1:
The patent applies preliminary action by computing error-detection codes (EDC) for both address and data before transmission occurs. The memory controller calculates EDC for the address and sends it to the memory device, which then computes EDC for the data using both the address and data as inputs. This pre-computation allows error detection capability to be built into the transmission process itself, enabling high-speed data transfer while maintaining reliability through proactive error detection rather than reactive correction.
2Reliability
If error detection mechanisms are added to improve reliability, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent merges error detection for both address and data into a unified EDC system. The memory device computes a single EDC value that is based on both the address and data inputs, rather than maintaining separate error detection mechanisms. This consolidation reduces device complexity by integrating multiple error detection functions into one cohesive process, while still providing comprehensive error detection capability for both address and data transmissions.
3Reliability
If address errors are detected and corrected to improve reliability, then data integrity is improved, but transmission latency increases
Solution Approach 1:
The patent implements feedback by having the memory device compute EDC based on both address and data, then transmit this combined EDC back to the memory controller for verification. The controller compares the received EDC with independently computed values to detect errors. This feedback mechanism enables real-time error detection without requiring retransmission, as the EDC is computed and verified as part of the original transmission sequence, thereby maintaining low latency while ensuring data integrity.
Data Source
AI summary
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.