DRAM Address Error Feedback for Write Cancellation
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Solution Overview
Problem
Modern memory systems face significant challenges in error detection and correction, particularly as data transfer rates increase, leading to issues with signal quality due to noise and inter-symbol interference, where address errors can be more detrimental than data errors, potentially corrupting stored data.
Innovation Solution
A mechanism is implemented in memory systems where the DRAM computes an error-detection code based on both address and data, which is then verified by the controller, allowing for the detection and prevention of erroneous write operations by canceling them, thus ensuring error-resistant transmission of both address and data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer rate is increased to improve productivity, then productivity is improved, but transmission errors increase due to noise and inter-symbol interference
Solution Approach 1:
The patent applies preliminary action by computing the error-detection code at the DRAM in advance based on the address before the write operation is executed. This allows the controller to verify the address integrity before committing to the write operation, preventing erroneous writes due to address errors that may occur at high data transfer rates.
Solution Approach 2:
The patent implements feedback by having the DRAM compute and return an error-detection code to the controller, which then verifies this code against its own computation. This feedback mechanism enables real-time detection of address errors without slowing down the overall data transfer rate, thus maintaining productivity while improving reliability.
2Reliability
If error detection code computation is performed to improve reliability, then reliability is improved, but latency increases
Solution Approach 1:
The error-detection code is computed in advance by the DRAM based on the address parameter alone, before the actual write operation proceeds. This preliminary computation allows for rapid verification without adding significant latency to the critical write path, as the computation uses simple bitwise operations rather than complex algorithms.
Solution Approach 2:
The patent changes the parameter used for error detection from including data (which would require waiting for data to be ready) to using only the address parameter. This parameter change enables the error detection to occur earlier in the pipeline, reducing latency while maintaining reliability.
3Reliability
If comprehensive error detection including both address and data is implemented to improve reliability, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the error detection into two parts: address error detection (performed by computing EDC based on address only at the DRAM) and data error detection (performed by comparing controller-computed EDC with DRAM-returned EDC). This segmentation allows the DRAM to perform simple address-based detection, reducing its complexity, while the controller handles the more comprehensive verification.
Solution Approach 2:
The DRAM performs self-service by computing its own error-detection code based on the address and returning it to the controller for verification. This self-service approach eliminates the need for complex external error detection circuitry, reducing overall device complexity while maintaining comprehensive error detection capability.
Data Source
AI summary
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.