DRAM Address Mapping to Contain Row Hammer Bitline Errors
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Solution Overview
Problem
The repetitive writing of data to a memory cell in DRAM can cause electrical, magnetic, or thermal interference with adjacent cells, leading to data corruption known as 'proximate charge disturbance' or 'row hammer', which legacy technologies struggle to effectively mitigate.
Innovation Solution
Implementing logical-to-physical (L2P) address mapping to shuffle bitline addresses across different dies in a DRAM module, ensuring that each die accesses a different physical address, thereby reducing the likelihood of simultaneous data corruption by distributing the impact of 'row hammer' attacks across multiple dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written repeatedly to the same memory cell, then data storage function is maintained, but electrical interference causes data corruption in adjacent cells
Solution Approach 1:
The patent divides the memory system into multiple independent dies (first die, second die, third die) with separate bitline mappings. Each die handles a portion of the address space, so that repetitive writes to a logical address affect different physical locations across dies. This segmentation isolates the harmful electrical interference to specific dies rather than allowing it to propagate system-wide, thereby maintaining overall data integrity.
Solution Approach 2:
The patent introduces a new dimension of address mapping by implementing die-level bitline shuffling where logical bitline addresses are mapped to different physical bitline addresses on different dies. This dimensional transformation of the addressing scheme ensures that repetitive access patterns in the logical space translate to dispersed physical access patterns across multiple dies, reducing cumulative electrical interference at any single location.
2Reliability
If logical-to-physical address mapping is implemented to distribute row hammer impact, then data corruption is limited, but address mapping complexity increases
Solution Approach 1:
The address mapping is segmented across multiple dies, with each die having its own bitline mapping table. This segmentation allows the complexity to be distributed and managed independently per die rather than requiring a monolithic mapping structure. Each die's mapping table can be optimized separately, reducing the overall system complexity while maintaining error correction capabilities.
Solution Approach 2:
The patent changes the mapping parameters by implementing die-specific bitline address transformations. Instead of a uniform mapping across all dies, each die applies parameter changes to its bitline addresses based on its identity and configuration. This allows flexible adaptation of the mapping scheme to reduce complexity while maintaining the desired error distribution properties.
Data Source
AI summary
Provided is a memory system including a memory module bank comprising a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells arranged in wordlines and bitlines and a memory controller configured to receive from a central processing unit (CPU) a data byte to be stored in a wordline of the memory module bank. Also included is a logical-to-physical address mapping block (L2P AMB) configured to map a logical bitline address of the data byte to a physical bitline address of a first memory cell array of the plurality of memory cell arrays, wherein a plurality of logical bitline addresses of the data byte are shuffled to different physical bitline memory addresses of the first memory cell array. Each respective memory cell array of the plurality stores a respective bit value, corresponding to a common logical bitline address, to a different respective physical bitline in each different respective memory cell array of the plurality.