DRAM Address Error Detection to Cancel Erroneous Memory Writes
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Solution Overview
Problem
Modern memory systems face significant challenges in error detection and correction, particularly as data transfer rates increase, leading to issues with signal quality due to noise and other factors, where address errors can be more detrimental than data errors, potentially corrupting stored data.
Innovation Solution
A mechanism is implemented in memory systems where the DRAM computes an error-detection code (EDC) based on both address and data, which is then verified by the memory controller, allowing for timely detection and correction of errors, including the ability to cancel erroneous write commands and optimize system latency and buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer rate is increased to improve productivity, then transmission errors increase due to noise and signal quality degradation
Solution Approach 1:
The patent applies preliminary action by computing the error detection code (EDC) in advance at the DRAM device before data transmission occurs. The EDC is calculated based on the data to be transmitted, allowing the memory controller to verify data integrity before committing to the transmission, thus preventing error propagation at higher data rates
2Reliability
If error detection code computation is performed on both address and data, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the error detection function into the existing DRAM device architecture, combining address and data validation into a unified EDC computation process. This integration allows both address and data to be protected without requiring separate error detection systems, thereby improving reliability while managing device complexity through consolidation
3Reliability
If error detection and correction mechanisms are implemented, then data integrity is improved, but system latency increases due to additional verification steps
Solution Approach 1:
The EDC computation is performed in advance at the DRAM device before data transmission, allowing the memory controller to verify data integrity proactively. This preliminary verification prevents the need for retransmissions and error correction delays, thereby maintaining data integrity while minimizing system latency
Solution Approach 2:
The DRAM device performs self-service by autonomously computing and providing the EDC without requiring external intervention from the memory controller. This self-contained error detection capability reduces the verification burden on the controller, thereby reducing overall system latency while maintaining data integrity
Data Source
AI summary
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.