DRAM Word Line Air Chamber Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor integration increases, parasitic capacitances between word lines and bit lines in DRAM structures grow, causing mutual interference and affecting electrical performance.
Innovation Solution
A method of manufacturing a semiconductor structure that involves forming a word line trench with a sacrificial structure including a horizontal portion, removing the horizontal portion to create an air chamber, which reduces parasitic capacitance between conducting wires and improves electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If integration of DRAM continuously increases to reduce volume, then device miniaturization is achieved, but parasitic capacitances between word lines and bit lines increase causing mutual interference
Solution Approach 1:
The patent extracts the problematic dielectric material from between the word line and bit line by creating an air chamber (vacuum region) in this space. By removing the dielectric material that causes parasitic capacitance and replacing it with air/vacuum, the harmful capacitive coupling is eliminated while maintaining the high integration density
Solution Approach 2:
The patent introduces air/vacuum as an intermediary substance between the word line and bit line. This intermediary has minimal dielectric properties compared to traditional insulating materials, thereby reducing parasitic capacitance while still providing electrical isolation. The air chamber acts as a mediator that allows close spacing without harmful capacitive effects
2Productivity
If spacing between word lines and between word line and bit line is reduced to increase integration, then device density is improved, but parasitic capacitances increase causing mutual interference
Solution Approach 1:
The patent removes the dielectric material from the critical region between word line and bit line, creating an air chamber. This extraction eliminates the source of parasitic capacitance while allowing the conductors to be positioned closer together, thereby achieving high integration density without harmful capacitive coupling
Solution Approach 2:
The patent applies different dielectric properties to different regions: traditional dielectric materials are used in regions where they provide benefit, while an air chamber (vacuum region with minimal dielectric properties) is created specifically in the region between word line and bit line where parasitic capacitance must be minimized. This localized quality change allows close spacing without harmful effects
Data Source
AI summary
The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a base, wherein the base includes an active region and a shallow trench isolation structure separating the active region, a word line trench is formed in the base, and the word line trench exposes a part of the active region and the shallow trench isolation structure; forming a first intermediate structure in the word line trenches, wherein the first intermediate structure covers side walls and a bottom wall of the word line trench, a first trench is formed in the first intermediate structure, the first intermediate structure includes a sacrificial structure, and the sacrificial structure includes a horizontal portion; and removing the horizontal portion of the sacrificial structure, and closing the first trench, and forming an air chamber.