DRAM Conductive Connection Structure With Air Gaps for Lower RC Delay
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Solution Overview
Problem
The shrinking size of Dynamic Random Access Memory (DRAM) memory cells results in large parasitic capacitance and RC delay due to the conductive connection structures, making it difficult to adjust resistance and cross-sectional area parameters effectively.
Innovation Solution
A semiconductor structure with a conductive layer having holes, where the inner wall is covered with a first dielectric layer with varying thickness, and a second dielectric layer that blocks the orifice, forming air gaps with larger sizes away from the orifice, which increases air filling and reduces parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of conductive connection structures is reduced to adapt to continuous shrinking of DRAM memory, then the memory density is improved, but the parasitic capacitance increases resulting in serious RC delay
Solution Approach 1:
The patent introduces air gaps (porous structure) within the conductive connection structure by forming voids between stacked conductive posts. This porous configuration reduces the parasitic capacitance by replacing high-dielectric material with air (low dielectric constant), thereby reducing RC delay while maintaining the reduced size for high memory density
Solution Approach 2:
The conductive connection structure employs a composite configuration combining multiple conductive posts stacked vertically with air gaps between them, rather than using a single solid conductor. This composite structure optimizes both the electrical performance (reduced capacitance) and spatial utilization (reduced footprint)
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively alleviates parasitic capacitance and RC delay, enhancing the storage performance of DRAM memory by optimizing the air gap structure and filling amount within the conductive connection structures.
Implementation Method 1
Air gaps are formed in the first dielectric layer and the second dielectric layer, and the size of the air gap on the side away from the orifice is larger than the size of the air gap on the side close to the orifice
Data Source
AI summary
The disclosed semiconductor structure includes a conductive layer, a channel in the conductive layer. The inner wall of the channel is covered with a first dielectric layer. The thickness of the first dielectric layer is greater at the orifice of the channel than the thickness on the side away from the orifice; the first dielectric layer on the side close the orifice is covered with a second dielectric layer, and the second dielectric layer blocks the orifice; an air gap is formed in the first dielectric layer and the second dielectric layer, and the size of the air gap on the side away from the orifice is larger than the size of the air gap on the side close to the orifice. The present application can effectively reduce the parasitic capacitance of the conductive connection structure, alleviate its RC delay problem, and optimize the storage performance of the memory.