DRAM-Aware Cache Controller Using Linked List Queues
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Solution Overview
Problem
Existing DRAM-aware scheduling techniques are insufficient to maximize efficiency in data caching, particularly in managing dirty cache data and optimizing data transfer to DRAM.
Innovation Solution
A system and method for controlling data caching that includes a cache controller system configured to receive transaction requests, store data in data storage structures organized like DRAM, and control data transfer to DRAM, using linked list queues to manage dirty cache lines and optimize eviction based on DRAM bank organization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional DRAM-aware scheduling techniques are used to manage cache data, then basic memory access efficiency is maintained, but data caching efficiency cannot be maximized and latency is reduced insufficiently
Solution Approach 1:
The patent segments the cache controller system into multiple specialized components: a data storage structure organized like DRAM with separate banks, a cache controller that manages eviction decisions, and a DRAM interface controller that handles data transfer. This segmentation allows each component to be optimized independently, enabling more efficient cache management and reduced latency compared to traditional monolithic approaches.
Solution Approach 2:
The patent implements preliminary action by proactively evicting dirty cache data to DRAM before the cache becomes fully occupied. The cache controller monitors cache usage and initiates eviction operations in advance, preventing cache overflow and potential write-back storms. This preliminary eviction strategy maintains cache efficiency and reduces latency by ensuring smooth data flow to DRAM.
2Quantity of substance
If cache memory fills or becomes dirty, then more data can be cached, but write-back or eviction operations are required which reduce efficiency
Solution Approach 1:
The patent ensures continuity of useful action by maintaining a steady stream of cache data evicted to DRAM. Rather than allowing the cache to fill up and then performing bulk evictions, the system continuously evicts dirty cache lines to DRAM in a controlled manner. This continuous operation prevents cache overflow, maintains high cache capacity utilization, and avoids efficiency losses from sudden write-back operations.
Solution Approach 2:
The patent introduces a DRAM interface controller as an intermediary between the cache controller and the DRAM. This intermediary manages the data transfer process, buffering and coordinating evicted cache data with DRAM write operations. By acting as a mediator, it smooths out the eviction process and prevents direct conflicts between cache operations and DRAM write-back requirements.
3Speed
If DRAM-aware scheduling is used to randomize bank selection, then sequential access latency is reduced, but efficiency is insufficient when managing dirty cache data
Solution Approach 1:
The patent applies local quality by organizing the data storage structure with separate DRAM banks that correspond to specific cache sets. Instead of using a single randomized bank selection approach, the system maps cache lines to specific DRAM banks based on their cache set affiliation. This localized mapping optimizes access patterns for dirty data eviction while maintaining the benefits of DRAM bank parallelism.
Solution Approach 2:
The patent changes the scheduling parameter from purely randomized bank selection to a deterministic bank assignment based on cache set mapping. This parameter change allows the system to optimize for dirty data management by directing evictions to specific DRAM banks that are best suited for receiving cache data, rather than using generic randomization. The parameter change maintains memory access speed while significantly improving dirty data management efficiency.
Data Source
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AI summary
Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.