DRAM Memory Background Refresh During Access Operations
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAM, face downtime and increased power consumption due to the need for frequent refresh operations to maintain data integrity, which makes them unavailable for access operations.
Innovation Solution
Implementing background refresh operations that allow refreshes to occur during access operations by determining refresh needs based on deficit counts and utilizing extended activation commands to overlap refresh and access times, reducing the number of stand-alone refreshes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed to maintain data integrity in DRAM memory cells, then data integrity is preserved, but the memory device becomes unavailable for access operations causing downtime
Solution Approach 1:
The patent merges refresh operations with access operations by allowing refresh to occur in the background during extended activation periods. When an access operation activates a word line, the system extends the activation time and uses this period to perform refresh operations on other banks or memory regions, combining what were previously separate operations into an integrated process that eliminates dedicated refresh downtime.
Solution Approach 2:
The patent implements continuous refresh operations by maintaining memory availability throughout the refresh process. Instead of stopping all access operations during refresh, the system continues to accept and process access requests while background refresh operates concurrently, ensuring that the memory device remains continuously useful without interruption or downtime.
2Reliability
If frequent refresh operations are performed to prevent charge decay in memory cells, then data integrity is maintained, but power consumption increases
Solution Approach 1:
The patent implements periodic refresh operations triggered by access patterns rather than continuous refreshing. The system monitors access operations and initiates background refresh only when appropriate conditions are met, such as during extended activation periods or when specific access patterns indicate the need for refresh. This periodic approach reduces unnecessary refresh operations and associated power consumption while maintaining data integrity.
Solution Approach 2:
The patent enables the memory system to perform refresh operations autonomously during background processing without requiring dedicated refresh cycles. The background refresh mechanism automatically manages refresh operations during normal access operations, allowing the system to service its own refresh needs without external intervention or additional power-intensive dedicated refresh periods.
3Reliability
If stand-alone refresh operations are performed to ensure all memory cells are refreshed, then complete refresh coverage is achieved, but memory availability for access operations is reduced
Solution Approach 1:
The patent combines stand-alone refresh operations with access operations by implementing background refresh that occurs concurrently with normal memory access. Instead of performing refresh separately from access operations, the system integrates refresh into the background processing during extended activation, merging two previously separate operational modes into a unified approach that maintains both refresh coverage and memory availability.
Solution Approach 2:
The patent makes the memory system multi-functional by enabling it to perform both access operations and refresh operations simultaneously through background refresh. The same memory infrastructure handles both data access and data maintenance tasks concurrently, allowing the system to serve multiple functions without requiring separate dedicated time periods for each operation, thereby maintaining high memory availability while ensuring complete refresh coverage.
Data Source
AI summary
A memory device receives a command, address, or combination thereof as part of an access operation which indicates an opportunity to perform a refresh background operation. The memory device may determine whether or not to perform the background refresh operation. If a background refresh operation is performed, the memory accesses a word line in a first section of a memory bank and refreshes a word line in a different section of the memory bank. In some embodiments, an opportunity background refresh operation may be signaled by an access command with an extended timing window.