DRAM Bank Partitioning With Partial ECC for Low-Power Refresh
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices consume significant power, especially during refresh operations, which limits battery life in portable devices like cellular telephones, where frequent data access is required, making it impractical to use existing reduced power refresh modes that delay data access or minimize power savings.
Innovation Solution
Implementing an error checking and correcting semiconductor device that refreshes infrequently accessed data at a low rate using ECC techniques, while maintaining frequently accessed data at a normal refresh rate without entering a reduced power refresh mode, allowing immediate access to critical data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DRAM memory cells are refreshed at a normal rate to ensure data integrity, then data reliability is maintained, but power consumption increases
Solution Approach 1:
The memory system is divided into two distinct segments: a first memory region that operates in low power mode with reduced refresh rates and ECC protection, and a second memory region that operates in normal mode with standard refresh rates. This segmentation allows different parts of the memory system to operate under different refresh strategies based on their specific requirements, thereby reducing overall power consumption while maintaining data integrity where needed.
Solution Approach 2:
Different refresh rates are applied to different regions of the memory device based on local requirements. The first memory region uses a reduced refresh rate suitable for infrequently accessed data, while the second memory region uses a normal refresh rate for frequently accessed data. This local differentiation optimizes power consumption by applying the appropriate refresh strategy to each region rather than using a uniform approach across the entire memory device.
2Use of energy by moving object
If the DRAM enters a reduced power refresh mode to save energy, then power consumption decreases, but data access time increases
Solution Approach 1:
The memory system separates frequently accessed data from infrequently accessed data into different memory regions. By placing frequently accessed data in the second memory region that operates in normal mode, the system ensures that critical data can be accessed immediately without the delays associated with low power mode transitions, while still allowing the first memory region to operate in power-saving mode.
Solution Approach 2:
Frequently accessed data is pre-positioned in the second memory region that maintains normal refresh rates and remains ready for immediate access. This preliminary arrangement ensures that when data is needed, it is already in the optimal location and state for quick retrieval, eliminating the need to exit low power mode for frequent accesses.
3Use of energy by moving object
If ECC techniques are applied to all data to enable reduced refresh rates, then power consumption decreases, but device complexity increases
Solution Approach 1:
ECC protection is selectively applied only to the first memory region that stores infrequently accessed data and operates in low power mode. The second memory region that stores frequently accessed data operates without ECC overhead. This selective application of ECC reduces the overall complexity of the system compared to applying ECC universally, while still enabling power savings in the low power mode region.
Solution Approach 2:
Instead of applying ECC protection to the entire memory device, the system applies ECC partially only where needed for the low power mode operation. This partial application of ECC reduces the complexity burden while achieving the power consumption benefits in the specific region that requires reduced refresh rates.
4Use of energy by moving object
If refresh rate is reduced to save power, then power consumption decreases, but data loss risk increases
Solution Approach 1:
The system applies different refresh strategies to different memory regions based on their specific requirements. The first memory region uses a reduced refresh rate combined with ECC protection, which together provide both power savings and data retention guarantees. The second memory region uses a normal refresh rate that inherently ensures data retention without requiring ECC. This local differentiation resolves the contradiction by providing appropriate protection in each region.
Solution Approach 2:
ECC syndrome information acts as an intermediary mechanism that enables the system to safely use reduced refresh rates. By introducing ECC as an intermediate layer of protection, the system can operate the first memory region at lower refresh rates without increasing data loss risk, as the ECC mechanism detects and corrects errors that would otherwise occur due to the reduced refresh frequency.
Data Source
AI summary
A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.