DRAM Bank Segmentation for Multiple Open Rows and Lower Latency
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Solution Overview
Problem
Conventional DRAM systems are limited to having only one row open per bank, which restricts performance and efficiency in memory operations.
Innovation Solution
Implementing a DRAM component that allows multiple rows to be open concurrently by dividing the address space into segments and using a controller to manage row address ranges, track blocked segments, and maintain a map of open rows to tag values, enabling simultaneous access to multiple rows within a bank.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If only one row is opened per bank in conventional DRAM systems, then the system structure remains simple, but memory performance and operational efficiency are restricted
Solution Approach 1:
The patent divides the address space of each bank into multiple segments, where each segment can independently track open row status. This segmentation allows multiple rows to be open concurrently in different segments while maintaining manageable complexity through structured address space organization.
Solution Approach 2:
The patent introduces a new dimension of control by adding segment identifiers to the traditional bank-row-column address structure. This enables multiple rows per bank to be distinguished and managed through the segment dimension, allowing concurrent access without confusion.
2Loss of time
If multiple rows are opened concurrently in a bank, then access latency is reduced and operational efficiency improves, but tracking and managing row addresses becomes more complex
Solution Approach 1:
By segmenting the address space and associating each segment with specific open row tracking, the patent reduces the complexity of managing multiple open rows. Each segment maintains its own open row status independently, simplifying the overall tracking mechanism compared to a unified approach.
Solution Approach 2:
The patent introduces segment identifiers as an intermediary layer between the bank level and row level. This intermediary structure facilitates efficient tracking and management of multiple open rows by providing a hierarchical organization that simplifies address resolution and status monitoring.
3Productivity
If multiple rows are opened concurrently, then memory throughput increases, but the risk of address conflicts and management errors increases
Solution Approach 1:
Segmentation isolates address management into independent segments, reducing the probability of conflicts. Each segment maintains its own open row state, ensuring that address management errors in one segment do not propagate to other segments, thereby improving overall reliability.
Solution Approach 2:
The patent implements feedback mechanisms where the controller continuously monitors the status of open rows within each segment and uses this information to make informed decisions about subsequent memory operations. This feedback loop prevents address conflicts by ensuring proper state management.
Data Source
AI summary
A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.