Multi-Composition DRAM Barrier Layer for Low Resistance
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Solution Overview
Problem
Existing DRAM cells with buried gates face defects due to limitations in fabrication technologies, leading to performance and reliability issues, despite their superior performance over conventional planar gate structures.
Innovation Solution
A DRAM device with a multi-composition barrier layer in the bit lines, where the layer is nitrogen-rich at the top and silicon-rich at the bottom, reducing resistance between the barrier layer and adjacent layers, and formed through an atomic layer deposition process with a varying ratio of tungsten silicon nitride (WSixNy) to enhance ohmic contact and crystal grain size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-composition barrier layer is used in bit lines, then the fabrication process is simple, but the resistance between the barrier layer and adjacent layers (polysilicon and metal conductive layer) is high
Solution Approach 1:
The barrier layer is segmented into multiple sub-layers with different compositions: a first barrier layer (WSiN) adjacent to the polysilicon layer and a second barrier layer (WN) adjacent to the metal conductive layer. This segmentation allows each sub-layer to be optimized for its specific interface, reducing overall resistance without excessive complexity
Solution Approach 2:
Different regions of the barrier layer are given different compositions tailored to their local requirements: the silicon-rich first barrier layer optimizes contact with polysilicon, while the nitrogen-rich second barrier layer optimizes contact with the metal conductive layer. This local optimization reduces resistance at each interface
2Device complexity
If the bit line height is reduced to simplify the device structure, then the device complexity is reduced, but the resistance and grain boundary issues become more significant
Solution Approach 1:
The composition parameters of the barrier layer are changed across its thickness, transitioning from silicon-rich at the bottom to nitrogen-rich at the top. This parameter gradient allows the barrier layer to maintain low resistance and good grain structure even when the overall bit line height is reduced
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces resistance and grain boundary issues, improving the reliability and performance of DRAM devices by simplifying the fabrication process and reducing the height of the bit line structure.
Implementation Method 1
formed through an atomic layer deposition process with a varying ratio of tungsten silicon nitride (WSixNy)
Data Source
AI summary
A dynamic random access memory (DRAM) device includes a substrate, plural buried gates and plural bit lines. The buried gates are disposed in the substrate along a first trench extending along a first direction. The bit lines are disposed over the buried gates and extending along a second direction across the first direction. Each of the bit lines includes a multi-composition barrier layer, wherein the multi-composition barrier layer includes WSixNy with x and y being greater than 0 and the multi-composition barrier layer is silicon-rich at a bottom portion thereof and is nitrogen-rich at a top portion thereof.