DRAM Bit Line Contact Structure Vertical Trench Alignment
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Solution Overview
Problem
The miniaturization of memory devices, such as DRAM, leads to challenges in forming bit line contact structures, resulting in reduced yield due to size and position inaccuracies, and increased complexity and cost in the lithography process.
Innovation Solution
A method for manufacturing DRAM that involves forming parallel bit line contact trenches and a bit line contact structure in a self-aligned manner, reducing the need for multiple masks and allowing precise control over the position and size of the bit line contact structure, thereby preventing short-circuits and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of the bit line contact hole is reduced to achieve miniaturization, then the memory device size is reduced, but the manufacturing precision and reliability deteriorate due to exposure failures and short-circuits
Solution Approach 1:
The patent transitions from forming bit line contact holes in the traditional horizontal plane to forming bit line contact trenches extending vertically into the substrate. This dimensional change allows the contact structure to achieve electrical connection through the dielectric layer via vertical etching, enabling miniaturization while maintaining controllable dimensions through vertical process parameters rather than horizontal lithography limits
Solution Approach 2:
The patent changes the geometric parameters of the bit line contact structure from horizontal circular holes to vertical rectangular trenches. This parameter transformation allows the use of different process control variables (etch depth, trench width, sidewall angle) that are more controllable and less susceptible to lithography resolution limits, thereby improving manufacturing precision while enabling smaller device footprints
2Ease of manufacture
If conventional lithography process is used for forming bit line contact holes, then the process can be implemented, but the device complexity and production cost increase due to process control difficulties
Solution Approach 1:
The patent performs preliminary patterning of the bit line contact trench positions before forming the actual contact structure. The trench locations are pre-determined based on bit line projections, and the self-aligned formation ensures that subsequent processing steps automatically align with these pre-established positions, simplifying the overall lithography process and reducing the number of alignment-critical steps
Solution Approach 2:
The bit line contact structure formation is made self-aligned to the bit line position, meaning the contact trench automatically positions itself relative to the bit line without requiring separate alignment operations. This self-service mechanism eliminates complex alignment procedures and reduces process complexity while maintaining manufacturing feasibility
Data Source
AI summary
A DRAM and its manufacturing method are provided. The DRAM includes a buried word line, a first dielectric layer, a bit line, and a bit line contact structure. The buried word line is formed in a word line trench of the substrate, and extends along a first direction. The first dielectric layer is formed in the word line trench, located on the buried word line, and has a top surface lower than the top surface of the substrate. The bit line contact structure is formed on the substrate, and has a bottom surface higher than the top surface of the first dielectric layer. The bit line is formed on the substrate and extends along a second direction perpendicular to the first direction.