DRAM Bit Line Patterning for Low Resistance and Smooth Edges
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Solution Overview
Problem
Forming DRAM bit lines with both low resistance and good line edge roughness simultaneously is challenging due to the difficulty in achieving these characteristics simultaneously in existing manufacturing processes.
Innovation Solution
A method involving implanting an inert species into a bit line metal layer to form an amorphized layer with a smaller grain size, depositing a film stack, etching to form a patterned stack, and thermally annealing to improve line edge roughness and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional DRAM bit line formation processes are used, then manufacturing simplicity is maintained, but line edge roughness deteriorates and resistance increases
Solution Approach 1:
The bit line formation process is divided into multiple sequential steps: depositing the metal layer, forming a first patterned film stack, performing a first etch, depositing a second patterned film stack, and performing a second etch. This segmentation allows each step to optimize specific parameters, resulting in improved line edge roughness while managing process complexity through systematic breakdown of the formation process.
Solution Approach 2:
The first patterned film stack is formed and etched before the second patterned film stack is deposited. This preliminary action establishes a foundation structure that guides subsequent processing, enabling better control over final line edge roughness and resistance characteristics through staged pattern transfer.
2Reliability
If conventional DRAM bit line formation processes are used, then process simplicity is maintained, but bit line resistance increases
Solution Approach 1:
The bit line formation is segmented into multiple etching stages with intermediate film deposition. This allows optimization of each etch step to minimize resistance while maintaining manufacturing feasibility through standardized process modules that can be integrated into existing fabrication sequences.
Solution Approach 2:
The process utilizes changes in film stack composition and structure between the first and second patterned film stacks. By adjusting material parameters and layer configurations, the etching process achieves better control over bit line resistance while keeping the overall manufacturing approach compatible with established DRAM fabrication techniques.
3Manufacturing precision
If multi-step patterning is performed, then line edge roughness is improved, but manufacturing complexity increases
Solution Approach 1:
The formation of first and second patterned film stacks is merged into a coordinated multi-step process where each stack serves a specific function in the overall pattern transfer. This merging allows optimization of line edge roughness through cumulative patterning effects while managing manufacturing efficiency by integrating the steps into a unified fabrication sequence rather than treating them as separate operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in reduced line edge roughness and lower bit line resistance, enhancing the performance of DRAM devices by improving etch uniformity and contact resistance.
Implementation Method 1
implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size
Implementation Method 2
thermally annealing the patterned film stack on the substrate
Data Source
AI summary
Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.