3D DRAM Bit Line Structure for Lower Resistance and Capacitance
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Solution Overview
Problem
The integration of DRAMs faces challenges with increased transistor sizes and limited transmission rates due to high bit line resistances and parasitic capacitance, which adversely affect performance.
Innovation Solution
The semiconductor structure incorporates bit lines with conductive bodies and dielectric layers, featuring protruding contact portions and dielectric coverage on side walls, reducing resistances and parasitic capacitance through increased volume and enhanced electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the integration level of DRAM is increased, then the plane size is reduced, but the transistor transmission rate is limited due to high bit line resistance
Solution Approach 1:
The bit line structure transitions from a conventional planar configuration to a three-dimensional structure with contact portions protruding upward from the substrate. This vertical dimensionality addition increases the effective conductive volume without occupying additional planar space, thereby reducing resistance while maintaining high integration density.
Solution Approach 2:
The bit line is constructed as a composite structure comprising a conductive body (such as metal or doped semiconductor) and a dielectric layer. This composite configuration optimizes both electrical conductivity through the conductive portions and electrical isolation through the dielectric coverage, simultaneously addressing resistance and parasitic capacitance issues.
2Quantity of substance
If the transistor size is reduced to increase integration level, then more transistors fit on the substrate, but the transmission rate becomes limited
Solution Approach 1:
The bit line incorporates vertical contact portions that extend upward from the substrate surface. This three-dimensional structure increases the effective cross-sectional area for current flow without consuming additional planar space, enabling faster transmission rates while maintaining high transistor density on the substrate.
Solution Approach 2:
The bit line structure modifies the resistance parameter by creating protruding contact portions with increased volume. This geometric parameter change reduces the electrical resistance of the bit line, thereby improving the transmission rate even as transistor sizes are reduced to increase the number of devices.
3Ease of manufacture
If conventional bit line structures are used, then manufacturing is simpler, but parasitic capacitance is high which limits performance
Solution Approach 1:
The bit line is formed as a composite structure with a conductive body and a dielectric layer covering its side walls. This configuration reduces parasitic capacitance by providing electrical isolation between adjacent bit lines while the conductive portions maintain low resistance. The structure can be integrated into existing fabrication processes through sequential deposition and patterning steps.
Solution Approach 2:
The dielectric layer acts as an intermediary material between adjacent conductive bit line bodies. This dielectric intermediary reduces the parasitic capacitance coupling between neighboring bit lines, improving signal integrity and transmission performance while maintaining manufacturing feasibility through standard dielectric deposition techniques.
Data Source
AI summary
Embodiments provide a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate; bit lines positioned in the substrate, where each of the bit lines includes a conductive body and a dielectric layer, the conductive body includes a body portion and a plurality of contact portions, the body portion extend along a first direction, the contact portions protrude from a side surface of the body portion facing away from a bottom of the substrate, the contact portions are arranged at intervals along the first direction, and the dielectric layer covers side wall surfaces on left and right sides of the body portion along an extension direction; and transistors positioned on top surfaces of the contact portions facing away from the body portion, and extension directions of channels of the transistors are perpendicular to a plane where the substrate is positioned.