DRAM Bit Line Air Gap Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As DRAM memory cell dimensions decrease, capacitive coupling leads to increased parasitic capacitance, reducing device speeds and impacting overall performance.
Innovation Solution
A method is developed to form semiconductor devices with air gaps between conductive lines, using dielectric structures to support bit lines and reduce parasitic capacitance by incorporating air gaps with low dielectric constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM memory cell dimensions are reduced to increase packing density, then memory storage capacity increases, but parasitic capacitance increases due to capacitive coupling
Solution Approach 1:
The patent introduces air gaps that segment the continuous dielectric material between bit lines, creating discrete isolated regions. This segmentation reduces the capacitive coupling area between adjacent bit lines while maintaining the overall memory cell structure, directly addressing the parasitic capacitance issue that arises from dimension reduction
Solution Approach 2:
The patent applies different dielectric properties locally by introducing air gaps (low dielectric constant) in specific regions between bit lines, while maintaining solid dielectric material in other areas. This local quality change reduces parasitic capacitance in the critical coupling regions without compromising the overall memory cell functionality or storage capacity
2Quantity of substance
If dimension requirements are decreased to increase packing density, then memory storage capacity increases, but device speed decreases due to increased parasitic capacitance
Solution Approach 1:
By segmenting the dielectric structure with air gaps, the patent reduces parasitic capacitance that slows down device operation. This allows the memory cells to maintain smaller dimensions for high density while achieving faster speeds by reducing the capacitive loading that would otherwise limit switching performance
Solution Approach 2:
The patent changes the dielectric constant parameter in the regions between bit lines by introducing air gaps (k≈1) instead of solid dielectric material (k>3). This parameter change reduces the time constant RC, thereby increasing device speed while maintaining the reduced dimension requirements for high storage capacity
3Speed
If air gaps are formed between bit lines to reduce parasitic capacitance, then device speed improves, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates air gaps during the preliminary stages of bit line formation, specifically during the conformal deposition and etch-back processes. By integrating air gap formation into these existing manufacturing steps rather than adding separate dedicated air gap creation steps, the method reduces the increase in manufacturing complexity while achieving the speed improvement from reduced parasitic capacitance
4Reliability
If dielectric structures are used to support bit lines, then bit line collapse is prevented, but device complexity increases
Solution Approach 1:
The patent makes the dielectric structures serve multiple functions: they provide mechanical support to prevent bit line collapse during fabrication and operation, and simultaneously function as the insulating layer that defines the air gaps for reducing parasitic capacitance. This multi-functionality reduces the need for additional dedicated support structures, thereby limiting the increase in device complexity while improving reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces parasitic capacitance and prevents bit line collapse, enhancing device speed and performance by utilizing dielectric structures as supports during formation.
Implementation Method 1
reduce parasitic capacitance by incorporating air gaps with low dielectric constant
Data Source
AI summary
A method for preparing a semiconductor device, includes: forming a first dielectric structure and a second dielectric structure over a semiconductor substrate; forming a conductive material over the first dielectric structure and the second dielectric structure, wherein the conductive material extends into a first opening between the first dielectric structure and the second dielectric structure; partially removing the conductive material to form a first bit line and a second bit line in the first opening; forming a first capacitor contact and a second capacitor contact in the first dielectric structure and the second dielectric structure, respectively; forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate; and forming a first capacitor and a second capacitor over the first capacitor contact and the second capacitor contact, respectively.