DRAM Bit Line Air Gap Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The reduction in size of dynamic random-access memory (DRAM) cells leads to increased parasitic capacitance, which reduces the speed of DRAM memory cells and negatively affects overall device performance due to capacitive coupling.
Innovation Solution
A method for manufacturing a semiconductor structure that involves forming bit lines on a substrate, creating a patterned layer and a conformal layer, forming a contact taller than the patterned layer, and removing the layers to create an air gap sealed by a dielectric layer, which helps in reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of DRAM memory cells is reduced to increase packaging density, then the packaging density is improved, but the parasitic capacitance increases due to capacitive coupling
Solution Approach 1:
The patent introduces an air gap as an intermediary space between adjacent bit lines. This air gap acts as a mediator that reduces the capacitive coupling between bit lines by replacing the traditional dielectric material with air, which has a lower dielectric constant. The air gap is formed by removing the patterned layer and conformal layer in specific regions, creating a controlled void space that minimizes parasitic capacitance while maintaining the close proximity needed for high-density packaging.
Solution Approach 2:
The patent changes the dielectric parameter between bit lines by replacing solid dielectric material with air. The dielectric constant of air (approximately 1.0) is significantly lower than that of traditional dielectric materials, thereby reducing the parasitic capacitance. This parameter change is achieved through selective removal of layers to create the air gap structure, allowing adjacent bit lines to be positioned closer together without proportionally increasing capacitive coupling.
2Area of stationary object
If the size of DRAM memory cells is reduced, then the packaging density is improved, but the speed of DRAM memory cells is reduced due to increased parasitic capacitance
Solution Approach 1:
The air gap serves as an intermediary that reduces the electrical interaction between adjacent bit lines. By introducing this air-filled space with low dielectric constant, the parasitic capacitance is minimized, allowing faster charging and discharging of the capacitor in the DRAM cell. This enables the memory cell to operate at higher speeds while maintaining the reduced size necessary for high packaging density.
3Object-generated harmful factors
If an air gap is created between the contact and bit line, then the parasitic capacitance is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The air gap structure is created through preliminary actions during the manufacturing process. Patterned layers and conformal layers are deposited and patterned in advance to define the future air gap regions. The sacrificial layers are positioned and dimensioned beforehand to ensure that when they are removed, the air gap will be formed at the correct location with the appropriate dimensions. This preliminary structuring simplifies the overall process by preparing the framework for air gap formation before the actual removal step.
Solution Approach 2:
The patent uses sacrificial layers (patterned layer and conformal layer) that are temporarily introduced during manufacturing and then discarded (removed) to create the air gap. These sacrificial layers serve their purpose during fabrication and are subsequently removed through etching processes, leaving behind the desired air gap structure. This approach allows complex three-dimensional air gap formation using standard semiconductor manufacturing techniques without requiring new equipment or processes.
Data Source
AI summary
The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a bit line on a substrate, forming a first dielectric layer over the substrate and surrounding a lower portion of the bit line, forming a second dielectric layer over the bit line and the first dielectric layer, forming a contact over the second dielectric layer, wherein a height of the contact above the substrate is greater than a height of the first dielectric layer above the substrate, removing the first dielectric layer and the second dielectric layer, and forming a third dielectric layer conformally over the bit line, the substrate and the contact, thereby forming an air gap between the contact and the bit line.