DRAM Bit Line Formation With CMP for Planar Buried-Gate Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for forming DRAM cells with buried gates often result in defects due to limitations in fabrication technologies, leading to performance and reliability issues, and there is a need for improved memory cells with enhanced performance and reliability.
Innovation Solution
A method of forming semiconductor memory devices with bit lines having planar top surfaces is developed, involving the formation of gates in a substrate, deposition of semiconductor layers, and a chemical mechanical polishing process to remove protruding etching profiles caused by the conductive layer, resulting in improved bit line contacts and stacked layers with planar top surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used to form DRAM cells with buried gates, then the manufacturing process is simpler, but defects are formed leading to poor performance and reliability
Solution Approach 1:
A planarization layer is formed over the conductive layer before completing the bit line structure, proactively addressing the topography issue before it causes defects. This preliminary action ensures a planar surface for subsequent processing steps, improving device reliability without fundamentally changing the fabrication approach
Solution Approach 2:
The planarization layer acts as an intermediary element between the conductive layer and the bit line structure. This intermediate layer absorbs the topography variations and provides a uniform surface, mediating the conflict between maintaining simple fabrication and achieving defect-free devices
2Manufacturing precision
If the conductive layer is deposited to fill the plug, then the bit line contact is formed, but protruding etching profiles are created causing non-planar top surfaces
Solution Approach 1:
The protruding portions of the conductive layer are selectively removed through etching back, extracting only the excessive material that causes non-planarity. This leaves the necessary conductive material in the plug region while removing the harmful protrusions, achieving both precise bit line contact formation and planar top surface
Solution Approach 2:
The topography of the conductive layer is changed from protruding to planar through controlled etching. By adjusting the etching parameters and using the planarization layer as a reference, the surface profile is transformed to achieve the desired planarity while maintaining electrical connectivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the creation of semiconductor memory devices with enhanced performance and reliability by ensuring planar top surfaces for bit lines and stacked layers, thereby simplifying the process flow and reducing defects.
Implementation Method 1
a chemical mechanical polishing process to remove protruding etching profiles caused by the conductive layer
Data Source
AI summary
A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.