DRAM Bit Line Contact Structure With Sacrificial Layer Gap Prevention
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Solution Overview
Problem
The formation of gaps in bit line (BL) contacts during the manufacturing of dynamic random access memory (DRAM) semiconductor structures leads to increased resistances and reduced transmission performance due to deep BL contact regions, which are a result of limitations in the deposition process.
Innovation Solution
The method involves controlling the thickness ratio of the sacrificial layer to the first initial conductive layer, etching the sacrificial layer completely to reduce the depth of BL contact regions, and depositing a second conductive layer to fill these regions, thereby avoiding gaps and improving transmission performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the BL contact region is made deeper to improve electrical connection, then the connection strength is improved, but gaps form during deposition which increases resistance
Solution Approach 1:
A sacrificial layer is formed at the bottom of the BL contact region before depositing the conductive layer. This preliminary structure enables complete filling of deep contact regions without gaps, as the sacrificial layer provides a foundation that allows subsequent conductive material to deposit uniformly throughout the entire contact depth.
Solution Approach 2:
The sacrificial layer acts as an intermediary structure during the deposition process. It mediates between the deep contact region geometry and the deposition process limitations by providing a temporary structure that facilitates complete material deposition, which is later removed to achieve the final contact structure.
2Manufacturing precision
If the sacrificial layer thickness is increased to ensure complete removal, then the etching completeness is improved, but the BL contact region becomes deeper which worsens gap formation
Solution Approach 1:
The thickness of the sacrificial layer is precisely controlled within a specific range (10-20 nm). This parameter optimization ensures that the layer is thick enough to be completely removed by etching while remaining thin enough to prevent excessive contact region depth that would cause gap formation during conductive layer deposition.
3Manufacturing precision
If the first initial conductive layer thickness is reduced to shallower depths, then gap formation is prevented, but the electrical connection capability is reduced
Solution Approach 1:
The conductive structure is divided into two separate layers: a first conductive layer retained from the initial layer and a second conductive layer deposited to fill the contact region. This segmentation allows the first layer to maintain adequate thickness for electrical capability while the second layer ensures complete filling and uniformity without gaps.
Solution Approach 2:
The first conductive layer and second conductive layer are combined to form a complete BL contact structure. The first layer provides the electrical connection capability maintained from the original structure, while the second layer adds the filling function to eliminate gaps, and together they achieve both uniformity and connection capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the resistances of BL contacts and enhances the transmission performance of the semiconductor structure by ensuring shallower BL contact regions and proper filling of the second conductive layer, ensuring effective electrical connections.
Implementation Method 1
removing, with the first mask layer as a mask, the sacrificial layer, a part of the first initial conductive layer and a part of the substrate
Implementation Method 2
forming a second conductive layer in the BL contact region, the second conductive layer filling the bit line contact region
Data Source
AI summary
The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The method of manufacturing the semiconductor structure includes: providing a substrate; forming, on the substrate, a first initial conductive layer, a sacrificial layer and a first mask layer with a pattern that are stacked sequentially, a thickness of the sacrificial layer being 10 nm-20 nm; and etching, with the first mask layer as a mask, the first initial conductive layer and the substrate to form a bit line (BL) contact region.