DRAM Bit Line Contact Planarization for Buried Gate Memory Cells
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Solution Overview
Problem
Existing DRAM cell fabrication technologies with buried gates face challenges due to defects caused by limitations in fabrication processes, leading to performance and reliability issues.
Innovation Solution
A method for forming semiconductor memory devices with bit lines having planar top surfaces is developed, involving the formation of a conductive layer with a peripheral top surface higher than its central top surface, followed by oxidation and removal of the oxide layer to create a plug with a planar top surface, thereby addressing the defects and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conductive layer is formed in the plug hole to replace the protruding etching profile, then the manufacturing precision is improved, but the device complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the conductive layer in advance to compensate for the protruding etching profile that will be created by the loading effect. The conductive layer is deposited before the etching process, and its thickness is carefully controlled to match the expected protrusion height, thereby pre-correcting the topography issue before it arises.
Solution Approach 2:
The patent utilizes parameter changes by adjusting the thickness of the conductive layer to precisely compensate for the protruding profile. By controlling the conductive layer thickness parameter, the method achieves planar top surfaces without requiring complex post-etching correction processes, thus improving manufacturing precision while managing device complexity.
2Measurement precision
If the loading effect of the conductive layer is considered to form protruding profiles, then the measurement precision is improved, but the ease of manufacture deteriorates
Solution Approach 1:
The patent converts the harmful loading effect into a beneficial tool for achieving planar surfaces. Instead of viewing the protruding profile caused by the loading effect as a defect to be eliminated, the method uses the predictable nature of this effect to guide the formation of the conductive layer, which is designed to create the exact opposite profile, thereby transforming the problem into a solution.
Solution Approach 2:
The patent applies preliminary anti-action by forming the conductive layer with a profile that is opposite to the expected protruding etching profile. The conductive layer is designed to have a depressed center and raised edges, which will counterbalance the protruding profile created during etching, thereby achieving a planar top surface through pre-compensation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively removes protruding etching profiles caused by the loading effect of the conductive layer, resulting in bit line contacts and stacked layers with planar top surfaces, enhancing the structure and performance of semiconductor memory devices.
Implementation Method 1
The peripheral top surface and the central top surface of the conductive layer are oxidized, to form an oxide layer
Data Source
AI summary
A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.