Staggered DRAM Bit Line Arrays for Lower Contact Resistance
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Solution Overview
Problem
As semiconductor devices shrink in size and integration level increases, the contact resistance between bit line contact structures and bit lines in DRAMs rises, reducing current flow and charge-discharge speed, leading to smaller sensing margins.
Innovation Solution
A bit line structure comprising two arrays of bit lines not aligned in the X direction, with enlarged cross-sectional areas for contact structures, allowing for reduced contact resistance and improved charge-discharge speed, achieved through specific manufacturing steps involving substrate preparation, interlayer dielectric formation, and patterning of conductive materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If semiconductor devices shrink in size to increase integration level, then device area is reduced, but contact resistance increases and charge-discharge speed decreases
Solution Approach 1:
The patent introduces a two-array bit line structure where first and second bit line arrays are arranged in different X-direction positions, extending in the Y-direction. This dimensional arrangement increases the cross-sectional area of contact structures without increasing the planar footprint, thereby reducing contact resistance while maintaining small device area.
Solution Approach 2:
The bit line structure is segmented into two separate arrays (first bit line array and second bit line array) with distinct contact structures. This segmentation allows each contact structure to be independently optimized for larger cross-sectional area, improving current flow and charge-discharge speed without compromising overall device integration.
2Area of stationary object
If semiconductor devices shrink in size to increase integration level, then device area is reduced, but charge-discharge speed decreases
Solution Approach 1:
By arranging bit lines in two arrays extending in the Y-direction with different X-direction positions, the patent creates larger cross-sectional contact areas that facilitate faster charge and discharge operations without increasing the planar device footprint.
Solution Approach 2:
The patent changes the geometric parameters of the contact structures by creating two arrays with different X-direction positions, thereby increasing the cross-sectional area parameter that directly influences charge-discharge speed while maintaining compact device dimensions.
3Reliability
If bit line contact structures are enlarged to reduce contact resistance, then contact resistance decreases, but device area increases
Solution Approach 1:
The patent resolves this contradiction by enlarging contact structures in the cross-sectional dimension (Y-direction extension) rather than in the planar dimension (X-Y plane), thereby reducing contact resistance without increasing the overall device footprint.
Solution Approach 2:
The patent applies local quality enhancement by concentrating the contact structure enlargement specifically in the Y-direction extension of the two arrays, providing larger cross-sectional area where needed for low contact resistance while keeping other areas compact for small device footprint.
Data Source
AI summary
A bit line structure, a manufacturing method thereof, and a semiconductor memory are provided. The bit line structure includes a first bit line array and a second bit line array. The first bit line array includes a plurality of first bit lines extending in a Y direction. The plurality of first bit lines have a same length and are aligned and arranged in an X direction. The second bit line array includes a plurality of second bit lines extending in the Y direction. The plurality of second bit lines have a same length and are aligned and arranged in the X direction. The first bit line array and the second bit line array are not aligned in the X direction. The X direction is perpendicular to the Y direction.