DRAM Bit Line Contact Stack for Low-Resistance 3D Arrays
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Solution Overview
Problem
In 3D DRAM devices, contact resistance (Rc) and contact stability are significant challenges due to the formation of impediments such as impurities, grain boundaries, and surface roughness, which affect the speed of data transfer and the overall performance of bit line contacts.
Innovation Solution
A method for forming bit line contacts in DRAM devices involves depositing a doped semiconductor layer over an exposed surface of a doped region of a substrate, followed by the deposition of a metal silicide layer and a nitride layer, all performed without breaking vacuum. This process includes pre-cleaning the substrate and forming a conductive layer over the nitride layer in separate chambers within the same processing system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition methods are used to form bit line contacts, then manufacturing process is simpler, but contact resistance increases due to impurities, grain boundaries, and surface roughness
Solution Approach 1:
The patent combines multiple deposition steps (doped semiconductor layer, metal silicide layer, and nitride layer) into a single continuous vacuum process without breaking vacuum between steps. This merging of processes prevents interface contamination and reduces contact resistance while maintaining manufacturing feasibility through integrated processing
Solution Approach 2:
The patent uses a vacuum environment throughout the deposition process to create an inert atmosphere that prevents oxidation and contamination of the deposited layers. This inert environment maintains high material quality and low contact resistance without requiring additional protective measures
2Manufacturing precision
If thin silicide layers are used in bit line contacts, then contact resistance decreases, but thermal stability deteriorates due to agglomeration and nucleation at high temperatures
Solution Approach 1:
The patent creates a composite contact structure consisting of a doped semiconductor layer, metal silicide layer, and nitride layer. This composite structure provides both low contact resistance (through the thin silicide layer) and high thermal stability (through the protective nitride layer that prevents agglomeration and nucleation at temperatures of 1050°C or more)
Solution Approach 2:
The nitride layer acts as an intermediary protective barrier over the thin silicide layer. This intermediary layer prevents direct exposure of the silicide to high temperatures, thereby preventing agglomeration and nucleation while allowing the thin silicide structure to maintain its low contact resistance properties
3Adaptability or versatility
If vacuum breaking occurs between deposition steps, then process flexibility increases, but interface contamination increases leading to higher contact resistance
Solution Approach 1:
The patent maintains continuous vacuum conditions throughout the deposition of the doped semiconductor layer, metal silicide layer, and nitride layer without breaking vacuum between steps. This continuity prevents interface contamination and ensures low contact resistance while the entire process is controlled through an integrated vacuum system that provides operational flexibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described method reduces contact resistance and improves thermal stability of bit line contacts, leading to enhanced performance in DRAM devices by minimizing interface contamination and maintaining high-quality deposited layers.
Implementation Method 1
depositing a doped semiconductor layer over an exposed surface of a doped region of a substrate
Implementation Method 2
A metal silicide layer is then deposited over the doped semiconductor layer
Implementation Method 3
exposed to a nitridation process to form a nitride layer over the metal silicide layer
Data Source
AI summary
The present disclosure generally relates to dynamic random access memory (DRAM) devices and to semiconductor fabrication for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and methods for forming CMOS contact, DRAM array bit line contact (BLC), and storage node structures. The integrated processing system and methods enable deposition of contact and storage node layers with reduced contamination and improved quality, thus reducing leakage current and resistance for the final contact and storage node structures.