DRAM Bit Line Contact Structure With 3D Conducting Layers
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Solution Overview
Problem
As semiconductor manufacturing processes advance, the decreasing size of DRAMs leads to increased contact resistance in bit line (BL) contact structures, hindering normal data reading and writing operations and affecting memory performance.
Innovation Solution
A semiconductor structure with buried word lines, grooves, bit line contact layers, insulating layers, and conducting layers is developed, where the insulating layers are selectively etched to increase the contact area between bit line conducting layers and contact structures, reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of memory becomes smaller to improve integration density, then integration density is improved, but contact area of BL contact structures becomes smaller and contact resistance increases
Solution Approach 1:
The patent transitions from a planar contact structure to a three-dimensional structure by forming grooves in the substrate and filling them with BL contact layers. The BL conducting layers then wrap around these vertical contact structures, utilizing the vertical dimension to increase contact area without expanding the horizontal footprint, thus maintaining high integration density while reducing contact resistance.
Solution Approach 2:
The patent implements a nested structure where BL contact layers are positioned within grooves in the substrate, and BL conducting layers envelop these contact layers. This nested arrangement maximizes the contact interface between conducting layers and contact structures within a compact volume, achieving both high integration density and low contact resistance.
2Ease of manufacture
If conventional BL contact structures are used in miniaturized memory, then manufacturing simplicity is maintained, but contact resistance increases and memory performance deteriorates
Solution Approach 1:
The patent divides the BL contact structure into distinct segments: grooves formed in the substrate, BL contact layers filling the grooves, and BL conducting layers covering the contact layers. This segmentation allows each component to be optimized independently while maintaining overall manufacturing simplicity and achieving reduced contact resistance for improved memory performance.
Data Source
AI summary
A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, in which a plurality of active areas arranged in an array are provided; buried word lines located in the substrate, in which each of the active areas intersects with two of the buried word lines; grooves located in an upper surface of the substrate, in which each of the grooves is located between two of the buried word lines in each of the active areas; bit line contact layers filling the grooves; insulating layers distributed between two of the grooves, in which a thickness between upper surfaces of the insulating layers and the upper surface of the substrate is smaller than a thickness between upper surfaces of the bit line contact layers and the upper surface of the substrate; and bit line conducting layers, covering the bit line contact layers and the insulating layers.