DRAM Bit Line Spacer Structure With Dual Air Gaps
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Solution Overview
Problem
Current semiconductor memory devices with recessed gate structures face challenges in increasing memory cell density and complexity in fabrication processes, which affects the efficiency and reliability of the devices.
Innovation Solution
The formation of two air gap layers between bit lines and storage node contacts using storage node pads as a mask to remove material layers, creating a bi-layered air gap structure that simplifies the process flow and reduces delay between resistor and capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased to meet high integration requirements, then storage capacity is improved, but fabrication process complexity increases
Solution Approach 1:
The patent introduces air gap layers that segment the bit line and storage node contact regions, creating distinct isolation zones. This segmentation allows for independent optimization of each component while maintaining high density, thereby reducing overall fabrication complexity despite increased memory cell density
Solution Approach 2:
The patent utilizes vertical air gap layers between bit lines and storage node contacts, adding a vertical dimension to the isolation structure. This dimensional approach enables high-density horizontal arrangement while maintaining electrical isolation through vertical separation, simplifying the fabrication process
2Reliability
If recessed gate structures are used to reduce leakage current, then reliability is improved, but fabrication difficulty increases
Solution Approach 1:
The patent forms air gap layers between bit lines and storage node contacts before final capacitor formation. This preliminary action establishes proper electrical isolation and structural definition early in the process, making subsequent recessed gate formation easier and more reliable
3Loss of time
If material layers are removed to form air gap layers, then delay between resistor and capacitor is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses storage node pads as intermediary masks to define the air gap regions. These pads serve as precise reference structures that automatically define the correct air gap dimensions and positions, reducing the need for separate precision alignment steps and lowering manufacturing precision requirements while achieving reduced signal delay
Data Source
AI summary
The present disclosure relates to a semiconductor memory device and a fabricating method thereof, and the semiconductor memory device includes a substrate, bit lines, plugs and a spacer structure. The bit lines are separately disposed on the substrate, and the plugs are also disposed on the substrate to alternately arrange with the bit lines. The spacer structure is disposed on the substrate, between each of the bit lines and each of the plugs. The spacer structure includes a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs. Therefore, two air gap layers may be formed between the bit lines and the storage node contacts to improve the delay between the resistor and the capacitor.