DRAM Bit Line Groove Structure for Lower Contact Resistance
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Solution Overview
Problem
The existing semiconductor structures face high contact resistance between bit lines (BLs) and BL plugs due to a limited contact area, which affects the performance of the semiconductor structure, particularly in DRAMs, leading to increased resistance and decreased signal propagation speed.
Innovation Solution
A semiconductor structure is designed with grooves on the surface of the BLs to increase the contact area with BL plugs, and the BLs are doped using a vapor doping process to reduce resistance, improving the overall performance by enhancing the contact area and reducing the BL resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the BL is placed horizontally beside the first stacked structure, then the transistor can be led out to the BL plug through the BL to be electrically connected to a peripheral circuit, but the contact resistance between the BL and the BL plug is large
Solution Approach 1:
The patent introduces a step structure that creates a vertical dimension in the contact interface between the BL and BL plug. The groove formed on the step surface of the BL allows the BL plug to make contact not only at the horizontal interface but also extends vertically into the groove, effectively transforming a 2D contact into a 3D contact volume, thereby increasing the contact area and reducing contact resistance
Solution Approach 2:
The BL plug is nested into the groove formed on the BL surface. This nesting structure allows the BL plug to be partially embedded within the BL contact region, maximizing the interfacial contact area between the two components and reducing the contact resistance through increased contact volume
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased contact area between BLs and BL plugs reduces contact resistance, improving the semiconductor structure's performance by enhancing data storage density and signal propagation speed.
Implementation Method 1
followed by vapor doping to reduce resistance
Data Source
AI summary
The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes: a substrate, a first stacked structure is disposed on the substrate, and includes a memory cell array; a plurality of word lines (WLs), arranged at intervals and extending along a first direction; a plurality of bit lines (BLs), arranged at intervals and extending along a second direction, one end of each of the plurality of BLs away from the memory cell array forms a step in the first direction, each BL is provided with a groove on a surface of the step, and the second direction and the first direction cross each other; and a plurality of BL plugs, arranged at intervals and extending along the first direction, one end of each BL plug is correspondingly disposed in the groove of one of the BLs.