DRAM Bit Line Insulating Stack Layout for Dense Memory Cells

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Solution Overview

Problem

The challenge in semiconductor memory devices with recessed gate structures is to increase memory cell density while improving fabrication efficiency and reliability, particularly in dynamic random access memory (DRAM) devices with reduced leakage current.

Innovation Solution

A semiconductor device design featuring a bit line structure with multiple insulating stacked structures having coplanar top surfaces and varying materials, enhancing insulating performance across different extending regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cell density is increased to meet high integration requirements, then storage capacity is improved, but fabrication process complexity and difficulty increase

Engineering Contradiction:

Improvememory cell densityVSAvoidfabrication process complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The bit line structure is segmented into multiple regions with different insulating stacked structures. Each region has insulating layers tailored to specific functional requirements, allowing high density in active areas while simplifying structures in peripheral areas, thus managing fabrication complexity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different insulating stacked structures are applied to different regions of the bit line. Active areas receive comprehensive insulating layers for high density operation, while peripheral areas have simplified structures, optimizing both density and fabrication ease in respective locations

Inventive Principle:

Principle #3Local quality

2Reliability

If insulating performance is enhanced in all regions, then reliability is improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:

Improveinsulating performanceVSAvoidstructure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different insulating stacked structures to different regions based on specific reliability requirements. Active areas receive full insulating layers for optimal performance, while peripheral areas have reduced structures, maintaining necessary reliability without uniform complexity throughout

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

Instead of applying uniform insulating structures across all bit line regions, the patent inverts the approach by using simplified structures in peripheral areas and comprehensive structures only where needed in active areas, reducing overall complexity while maintaining critical reliability

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS20260059741A1Semiconductor device

Publication Date: 2026.02.26 FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD

AI summary

The present disclosure includes a semiconductor device and a method of fabricating the same, with the semiconductor device including a substrate, a shallow trench isolation and a plurality of bit line structures. The substrate includes a plurality of active areas. The shallow trench isolation is disposed in the substrate and includes a first insulating layer and a second insulating layer. The bit line structures are disposed on the substrate. At least one of the bit line structures intersects the active areas, the first insulating layer and the second insulating layer, and respectively includes a first insulating stacked structure, a second insulating stacked structure and a third insulating stacked structure over the active areas, the first insulating layer and the second insulating layer, with each insulating stacked structure include a top surface being coplanar with each other and different stacked materials from each other.