DRAM Bit Line Mask Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As DRAM device sizes shrink, parasitic capacitance between the landing pad of the capacitor and the adjacent bit line increases, affecting electrical performance. Additionally, uneven film layers can cause undesired protrusions and damage to the bit line structure, leading to poor structural contour or line breakage.
Innovation Solution
The DRAM device incorporates a stacked structure with a mask structure comprising different dielectric layers (first dielectric layer, second dielectric layer with a lower dielectric constant, and third dielectric layer) to reduce parasitic capacitance and improve electrical performance. The method involves forming a bit line structure, a mask structure, and a spacer structure to ensure electrical connection and reduce capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the device size is reduced to increase integration density, then the area occupied by components is reduced, but the parasitic capacitance between the landing pad and bit line increases
Solution Approach 1:
A landing pad structure is introduced as an intermediary component between the capacitor and the bit line. This landing pad includes a first landing pad portion and a second landing pad portion that are laterally separated from the bit line, with a lateral separation distance of 0.5 micrometers or more. The landing pad structure acts as a mediator to reduce the parasitic capacitance coupling between the capacitor and the bit line while maintaining the compact device footprint.
Solution Approach 2:
The patent utilizes vertical stacking in the third direction (z-direction) to achieve lateral separation in the first and second directions (x-y plane). The first landing pad portion is positioned at a first height and the second landing pad portion is positioned at a second height, creating spatial separation in multiple dimensions. This multi-dimensional arrangement reduces parasitic capacitance without increasing the planar footprint of the device.
2Reliability
If the thickness of the hard mask layer is increased to protect the bit line material layer, then the bit line structure integrity is improved, but the ion implantation range and depth in the peripheral region cannot be achieved
Solution Approach 1:
The mask structure is segmented into multiple functional layers: a hard mask layer for protection, a first spacer layer for defining the bit line width, and a second spacer layer for additional protection and alignment. This segmentation allows each layer to perform its specific function optimally without interfering with the ion implantation process in the peripheral region, as the spacers are formed after the implantation steps.
Solution Approach 2:
The bit line structure is formed with the hard mask layer and spacer layers in advance before the ion implantation process in the peripheral region. This preliminary formation of protective layers ensures that the bit line material layer is protected from damage during subsequent processing steps, while the ion implantation in the peripheral region can proceed with the original mask layer thickness without requiring adjustment.
3Area of stationary object
If the lateral distance between the landing pad and bit line is reduced to increase integration density, then the area is reduced, but the parasitic capacitance increases
Solution Approach 1:
The patent achieves separation between the landing pad and bit line by utilizing the vertical dimension (third direction). The first landing pad portion is positioned at a first height level and the second landing pad portion is positioned at a second height level, creating vertical separation while maintaining compact planar footprint. This multi-dimensional spatial arrangement reduces parasitic capacitance coupling without increasing the lateral area occupied by the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance and improves the electrical performance of the DRAM device by minimizing the impact of uneven film layers and ensuring the integrity of the bit line structure, thereby enhancing yield and reducing production costs.
Implementation Method 1
the dielectric constant of the second dielectric layer is less than the dielectric constant of the first dielectric layer and the dielectric constant of the third dielectric layer
Data Source
AI summary
A dynamic random access memory device includes a substrate having an active area, a stacked structure and a capacitor contact structure. The stacked structure is formed over the substrate and includes a bit line structure, a mask structure and a spacer structure. The bit line structure on the substrate is electrically connected to the active area. The mask structure is formed on the bit line structure and includes the first, second and third dielectric layers that are sequentially formed on the bit line structure. The dielectric constant of the second dielectric layer is less than the dielectric constant of each of the second and third dielectric layers. The spacer structure is formed on sidewalls of the bit line structure and the mask structure. The capacitor contact structure formed on the substrate is laterally separated from the stacked structure. The capacitor contact structure is electrically connected to the active area.