DRAM Bit Line Formation With Planar Contacts Over Buried Gates
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Solution Overview
Problem
Current DRAM cell fabrication technologies with buried gates face defects due to limitations in fabrication, leading to performance and reliability issues, necessitating an improved method for forming bit lines with planar top surfaces to enhance memory device performance.
Innovation Solution
A method involving the formation of gates in a substrate, followed by a semiconductor layer and plug creation, with a deposition process to form a stacked structure, and subsequent etching and chemical mechanical polishing to achieve bit lines with planar top surfaces, addressing the loading effect of the conductive layer and ensuring even surfaces for the barrier and conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar gate structure is used, then fabrication process is simpler, but current leakage is increased and performance is reduced
Solution Approach 1:
The gate structure is segmented into a buried gate portion extending in the first direction and a fin gate portion extending in the second direction perpendicular to the first direction. This segmentation allows the device to combine the current leakage reduction benefits of buried gates with the performance advantages of fin gates, resolving the contradiction between reliability and device complexity.
2Manufacturing precision
If etching back process is performed without compensation, then conductive layer is removed, but protruding etching profiles are formed due to loading effect
Solution Approach 1:
A sacrificial layer is formed prior to the etching back process to compensate for the loading effect of the conductive layer. This preliminary action ensures that when the etching back is performed, the sacrificial layer maintains the planar top surface of the bit line contacts, preventing protruding etching profiles and achieving the desired manufacturing precision.
Solution Approach 2:
The sacrificial layer acts as an intermediary element between the conductive layer and the etching process. It absorbs the loading effect of the conductive layer during etching back, thereby protecting the bit line contact top surface from forming protruding profiles and simplifying the overall manufacturing process.
3Productivity
If stacked structure is formed directly without planarization, then deposition is faster, but non-planar surfaces cause defects in subsequent layers
Solution Approach 1:
The planar top surface of the bit line contacts is established in advance through the sacrificial layer method before the stacked structure (barrier layer and conductive layer) is formed. This preliminary planarization ensures that subsequent deposition processes can proceed at high speed without causing defects, as the planar base surface prevents irregularities in the stacked layers.
Solution Approach 2:
The sacrificial layer serves as a mediator that enables both high deposition speed and surface planarity. By maintaining a planar top surface during the deposition of the stacked structure, it allows fast deposition without compromising manufacturing precision, thus resolving the contradiction between productivity and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the creation of semiconductor memory devices with improved performance and reliability by ensuring bit lines and stacked layers have planar top surfaces, simplifying the process flow and reducing defects.
Implementation Method 1
a deposition process is performed to from a stacked structure on the semiconductor layer
Implementation Method 2
the additionally performed chemical mechanical polishing process and cleaning process rather before or after etching back the conductive layer
Data Source
AI summary
A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.