DRAM Bit Line Structure With Self-Aligned Spacer Support
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Solution Overview
Problem
In Dynamic Random Access Memory (DRAM) manufacturing, the miniaturization of device sizes leads to thin bit line walls that are prone to distortion or inclination, causing issues with the sidewall spacer layer's ability to wrap the bit line properly and affecting the performance by preventing adequate wire filling between transistors and capacitors.
Innovation Solution
A manufacturing method involving the formation of first patterns with flank walls on a substrate, followed by a filling layer that covers these flank walls and fills gaps between patterns, and subsequent etching to create second main bodies with protrusions, ensuring the sidewall spacer layer can self-align and maintain structural integrity during etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device sizes are miniaturized to achieve higher integration levels, then productivity and integration density are improved, but the bit line wall becomes thin and prone to distortion or inclination
Solution Approach 1:
A mandrel structure is formed beforehand on the bit line before depositing the sidewall spacer layer. This preliminary structure provides mechanical support during subsequent etching processes, preventing the thin bit line wall from distorting or inclining, thus maintaining manufacturing precision while enabling continued miniaturization for higher integration density
Solution Approach 2:
The mandrel acts as an intermediary structure between the thin bit line wall and the etching process. It provides temporary mechanical reinforcement during critical manufacturing steps, allowing the thin wall to maintain its shape without requiring thicker walls that would reduce integration density
2Productivity
If the bit line wall becomes thin due to miniaturization, then integration density is improved, but the sidewall spacer layer cannot properly wrap the bit line
Solution Approach 1:
The mandrel is formed on the bit line before the sidewall spacer layer deposition. This preliminary structure creates a broader surface area for the spacer layer to deposit upon, ensuring proper wrapping and adhesion even when the actual bit line wall is thin, thus maintaining reliability while enabling high integration density
3Productivity
If the bit line wall is thin, then device miniaturization is achieved, but wire filling between transistor and capacitor is inadequate
Solution Approach 1:
The mandrel structure is established before wire filling operations. It provides a stable reference structure and proper spacing that ensures adequate wire filling between transistor and capacitor components, maintaining manufacturing precision even as device dimensions are reduced for higher integration density
Data Source
AI summary
A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure includes: providing a substrate; forming on an upper surface of the substrate first patterns each including a first main body and a first flank wall covering a sidewall of the first main body; forming a filling layer which covers the first flank wall and fills a gap between adjacent first patterns; and etching a top of each of the first patterns to obtain second main bodies, second flank walls and protrusions located on upper surfaces of the second flank walls, the second flank wall covering a sidewall of the second main body, and a top of the protrusion being at least higher than a top of the second main body.