Embedded DRAM Bit Line Structure for Low Resistance Stability
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Solution Overview
Problem
As semiconductor technology advances, achieving high-speed, high-integration-density memory devices with low power consumption requires addressing the structural stability and resistance issues, particularly for DRAMs with dimensions smaller than 20 nm, where the shrinking dimensions pose significant challenges in maintaining electrical properties and resistance.
Innovation Solution
A semiconductor structure and manufacturing method involving the formation of trench structures, bit line contact and protection structures, and capacitor contact assemblies, where bit line structures are embedded into the substrate, reducing external height and trench depth, and capacitor contact structures are designed to enhance filling quality and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the key dimension of the semiconductor structure is shrunk to achieve high integration density, then the integration density is improved, but the structural stability and electrical properties of the bit line deteriorate
Solution Approach 1:
The bit line structure transitions from a planar configuration to a three-dimensional embedded structure within trench structures. The bit line is positioned at different depths within the substrate, creating a vertical dimension that allows for better mechanical support and electrical performance while maintaining high integration density through compact lateral arrangement.
Solution Approach 2:
The bit line structure is nested within the trench structure, which itself is embedded in the substrate. The bit line contact structure is positioned within the trench, and the bit line is formed within the trench structure, creating a nested configuration that provides structural stability while maintaining compact footprint for high integration density.
2Quantity of substance
If the key dimension of the semiconductor structure is shrunk to achieve high integration density, then the integration density is improved, but the resistance of the bit line increases
Solution Approach 1:
The bit line structure employs composite material configuration with conductive materials formed in the trench structure. The bit line contact structure uses materials with low resistance properties, and the bit line itself is formed with conductive materials that maintain low resistance despite the shrunk dimensions, achieving both high integration density and acceptable electrical resistance.
Solution Approach 2:
By positioning the bit line within the vertical dimension of the trench structure rather than solely in the lateral plane, the electrical path is optimized. The embedded configuration allows for shorter current paths and better electrical contact, reducing resistance while maintaining high integration density through compact lateral arrangement.
3Area of stationary object
If the bit line structure is formed with high integration density, then the device size is reduced, but the structural stability of the bit line deteriorates
Solution Approach 1:
The bit line is positioned within the vertical dimension of the trench structure, utilizing the depth of the substrate to provide mechanical support. This three-dimensional configuration allows the bit line to be mechanically anchored within the substrate, enhancing structural stability while maintaining compact lateral footprint for small device size.
Solution Approach 2:
The bit line is nested within the trench structure that is formed in the substrate. This nested configuration provides mechanical support from the surrounding substrate material, stabilizing the bit line structure while maintaining compact device footprint through efficient vertical space utilization.
Data Source
AI summary
A semiconductor structure and a manufacturing method thereof are provided. The method includes following operations. A substrate including active regions and isolation regions is provided. First trench structures are formed on the substrate, the first trench structure passing through the active region and the isolation region. Bit line contact structures are formed in the first trench structures. Bit line structures are formed on the bit line contact structures, at least part of the bit line structure being positioned in the first trench structure. Bit line protection structures are formed on the bit line structures, the bit line protection structure at least covering an upper surface of the bit line structure. Capacitor contact assemblies are formed, the capacitor contact assembly including a first capacitor contact structure and a second capacitor contact structure which covers an upper surface and part of a side wall of the first capacitor contact structure.