DRAM Bit Line Structure With Staggered Heights for Lower Capacitance
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Solution Overview
Problem
The decreasing distance between adjacent bit line structures in Dynamic Random-Access Memory (DRAM) leads to increased parasitic capacitance and affects the saturation current and running efficiency, necessitating a method to increase the distance between bit line structures without altering their arrangement.
Innovation Solution
The method involves forming bit line contact layers at different heights, with conducting layers on top surfaces having varying heights perpendicular to the word line structures, and etching these layers to create separate bit line structures with oblique connections, thereby increasing the distance between conducting layers without changing the bit line structure arrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between adjacent bit line structures is decreased to increase memory density, then the memory capacity is improved, but the parasitic capacitance between bit line structures increases
Solution Approach 1:
The patent introduces a vertical dimension by forming conducting layers at different heights (first conducting layer at a first height, second conducting layer at a second height different from the first height). This multi-level stacking approach increases the vertical distance between adjacent bit line structures, thereby reducing parasitic capacitance while maintaining high memory density through efficient space utilization in the vertical direction.
Solution Approach 2:
The patent changes the spatial parameter of the conducting layers by positioning them at different heights vertically. The first conducting layer is formed at a first height and the second conducting layer is formed at a second height, creating a vertical separation that reduces the electromagnetic coupling and parasitic capacitance between adjacent bit line structures while maintaining the horizontal arrangement for high density.
2Object-generated harmful factors
If the distance between bit line structures is increased to reduce parasitic capacitance, then the parasitic capacitance is reduced, but the memory density decreases
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension through multi-level stacking. Instead of increasing horizontal distance between bit line structures (which would reduce density), the patent forms conducting layers at different vertical heights, achieving parasitic capacitance reduction through vertical separation while maintaining high horizontal density.
Solution Approach 2:
The patent implements a nested structure where multiple conducting layers are stacked vertically within the same horizontal footprint. The first conducting layer and second conducting layer are positioned at different heights, creating a nested vertical arrangement that maximizes space utilization and maintains high memory density while reducing parasitic capacitance through vertical separation.
3Device complexity
If the conducting layers are formed at the same height to simplify the manufacturing process, then the manufacturing complexity is reduced, but the parasitic capacitance increases
Solution Approach 1:
The patent introduces vertical separation by forming conducting layers at different heights, which adds a dimensional parameter to the structure. This vertical stacking approach reduces parasitic capacitance through increased spatial separation while the patent maintains manufacturing simplicity by using sequential formation processes and standard photolithography techniques.
Solution Approach 2:
The patent employs preliminary patterning actions where photolithographic mask layers are formed with specific patterns (including angled patterns at 45 degrees or 135 degrees relative to word line structures) before conducting layer deposition. This preliminary masking approach enables the formation of multi-level conducting layers at different heights through controlled etching and deposition steps, reducing parasitic capacitance while maintaining manufacturing feasibility.
Data Source
AI summary
A method for forming a memory device includes: providing a substrate including at least word line structures and active regions, and a bottom dielectric layer and bit line contact layers that are on a top surface of the substrate; part of the bit line contact layers are etched to form bit line contact layers at different heights; conducting layers are formed, top surfaces of the conducting layers being at different heights in a direction perpendicular to an extension direction of the word line structure, and the top surfaces of the conducting layers being at different heights in the extension direction of the word line structure; top dielectric layers are formed; and etching is performed to form separate bit line structures.