DRAM Bit Line Void Sealing to Protect Peripheral Regions
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Solution Overview
Problem
Existing dynamic random access memory (DRAM) manufacturing processes suffer from structural abnormalities in the peripheral region due to patterning issues, leading to reduced device yields and damage to internal circuits.
Innovation Solution
A manufacturing method involving the use of a mask layer to protect the peripheral region during etching, forming a void between bit line structures, and applying a sealing layer to enhance structural support, while using isolation layers to prevent short circuits and improve yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a patterning process is performed on the array region, then the bit line structures are formed, but structural abnormalities occur in the peripheral region reducing device yields
Solution Approach 1:
A mask layer is introduced as an intermediary protective element between the etching process and the peripheral region structures. This mask layer absorbs the harmful effects of the etching process, preventing direct damage to the stacked film layer and internal circuits in the peripheral region while allowing the patterning process to proceed in the array region.
Solution Approach 2:
The mask layer is formed in advance before the etching process to preemptively protect the peripheral region. By preparing this protective barrier beforehand, the patent prevents structural abnormalities from occurring during the patterning process, thereby maintaining device yields without compromising bit line structure formation.
2Reliability
If etching is performed to form voids between bit line structures, then parasitic capacitance is reduced, but the peripheral region may be damaged
Solution Approach 1:
The mask layer serves as a protective intermediary that allows the etching process to create voids between bit line structures for parasitic capacitance reduction while preventing the etching process from damaging the peripheral region. The mask layer selectively protects areas where damage would be harmful while permitting necessary etching in the array region.
3Ease of manufacture
If the peripheral region is left exposed during manufacturing, then access is easier, but internal circuits are vulnerable to damage
Solution Approach 1:
The mask layer acts as a protective intermediary that covers the peripheral region during manufacturing processes. This protective barrier maintains easy access for manufacturing operations while simultaneously shielding internal circuits from damage caused by patterning and etching processes.
Data Source
AI summary
Disclosed are a memory, a semiconductor structure, and a manufacturing method thereof. The manufacturing method includes: providing a substrate, where the substrate includes bit line structures, a first isolation layer covering sidewalls of the bit line structures and a second isolation layer covering a surface of the first isolation layer; removing the second isolation layer on a top of the first isolation layer to expose the top of the first isolation layer, and removing the first isolation layer so as to form a void between the bit line structure and the second isolation layer; and forming a sealing layer covering an opening of the void.