DRAM Bit-Line Taper Structure to Prevent Void-Induced Shorts
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Solution Overview
Problem
In dynamic random access memory (DRAM), the reduction in wiring pitch leads to increased vertical structure dimensions, causing stress and potential voids between structures when insulating materials are embedded, which can result in conductive material infiltration and short circuits between wiring.
Innovation Solution
The semiconductor device incorporates taper-shaped segments in the upper portions of bit-line structures to widen the gap between adjacent bit-line structures, ensuring complete filling of insulating material and preventing void formation, thereby avoiding short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the wiring pitch is reduced to increase integration density, then the degree of integration is improved, but stress concentration occurs in the horizontal direction and voids form between structures
Solution Approach 1:
The patent applies asymmetry by giving the bit-line structures different widths at different heights. The upper portion has a larger width than the lower portion, creating an asymmetric tapered shape that widens the gap between adjacent structures at the upper level where stress concentration and void formation are most problematic. This asymmetric design allows sufficient spacing for complete insulating material filling while maintaining high integration density at the lower level.
Solution Approach 2:
The patent changes the geometric parameters of the bit-line structures by varying the width dimension along the vertical axis. The width parameter transitions from a smaller value at the lower portion to a larger value at the upper portion, creating a tapered profile. This parameter change resolves the contradiction by providing adequate horizontal spacing at the critical upper region while preserving compact dimensions at the lower region for high density.
2Quantity of substance
If structures are made long in the vertical direction to accommodate reduced wiring pitch, then integration density is improved, but stress concentration in the horizontal direction causes tapering and void formation
Solution Approach 1:
The asymmetric tapered shape of the bit-line structures addresses stress concentration by providing extra horizontal width at the upper portion where stress is most concentrated. This asymmetric design creates a stress-distributing geometry that prevents the horizontal narrowing that would otherwise occur, thereby preventing void formation while maintaining vertical structure length for high integration.
Solution Approach 2:
The patent applies beforehand cushioning by pre-designing the upper portion of the bit-line structures with increased width before the insulating material embedding process. This proactive geometric modification creates a cushion of additional space that prevents stress concentration from causing tapering and void formation during subsequent manufacturing steps, ensuring structural integrity throughout the process.
3Stability of the object's composition
If insulating material is embedded between vertical structures to maintain spacing, then structural stability is improved, but voids form when the space between structures is not completely filled
Solution Approach 1:
The asymmetric tapered shape with wider upper portions directly addresses the filling completeness issue by creating a geometric configuration that facilitates complete insulating material deposition. The increased horizontal width at the upper level provides sufficient space for the insulating material to be fully embedded without forming voids, while the lower portion maintains tighter spacing for high density. This design ensures both structural stability and manufacturing precision.
Data Source
AI summary
An apparatus includes a plurality of bit-line structures elongating in parallel in a first direction, each of the plurality of bit-line structures having a conductive portion and an insulating portion on the conductive portion; wherein the insulating portion of each of the plurality of bit-line structures includes taper-shaped segments and less taper-shaped segments, which appear alternately along the first direction.