DRAM Memory Cell Bonding Interface With Air Voids for Heat Isolation
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is minimizing the impact of heat treatment on the electrical characteristics of DRAM memory cells, which can be affected by the formation of other functional elements, leading to potential changes in performance.
Innovation Solution
The solution involves creating the transistor and storage capacitor portions separately and then joining them using a fusion bonding method, with an interface structure featuring air holes that connect cavity regions to the atmosphere, allowing for a depressurized environment and reducing the need for heat treatment, thereby minimizing the impact on the access transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If heat treatment is performed during the formation of functional elements, then the manufacturing process can be completed, but the electrical characteristics of transistors and storage capacitors will change
Solution Approach 1:
The memory cell structure is divided into separate transistor portion and storage capacitor portion formed on different substrates. This segmentation allows independent processing of each portion, enabling the transistor to undergo heat treatment without affecting the storage capacitor's electrical characteristics, thus resolving the contradiction between manufacturing completion and electrical characteristic preservation
Solution Approach 2:
A bonding interface with air holes is introduced as an intermediary structure between the transistor substrate and storage capacitor substrate. The air holes maintain pressure differential that prevents detachment during processing while allowing the bonding interface to transmit mechanical stress uniformly, enabling heat treatment without compromising electrical characteristics
2Reliability
If separate transistor and storage capacitor portions are created and joined later, then the influence of heat treatment is reduced, but the device structure becomes more complex
Solution Approach 1:
The bonding interface structure serves multiple functions simultaneously: it provides mechanical bonding between substrates, maintains pressure differential through air holes to prevent detachment, and enables uniform stress transmission during heat treatment. This multi-functionality reduces the need for additional specialized structures, thereby limiting the increase in device complexity while achieving heat treatment resistance
3Productivity
If fusion bonding method is used to join separate portions, then heat exposure is reduced and yield improves, but detachment during processing may occur
Solution Approach 1:
The bonding process utilizes controlled pressure differential parameter changes. By maintaining higher pressure on one substrate side and creating air holes at specific locations, the pressure differential creates a clamping force that enhances bonding strength during processing. After processing, equalizing the pressure prevents detachment, thus improving yield without compromising bonding strength
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the yield and performance of the semiconductor device by avoiding unwanted heat treatment, preventing the collapse of storage capacitors, and enhancing the stability of the memory cell structure, resulting in improved electrical characteristics and cost savings.
Implementation Method 1
air holes that connect cavity regions to the atmosphere, allowing for reduced heat exposure and improved yield by maintaining a depressurized environment during processing
Implementation Method 2
joining them using a fusion bonding method
Data Source
AI summary
An apparatus includes a base structure having a first portion including a plurality of transistors and a second portion surrounding the first portion; a storage structure on the first portion of the base structure, the storage structure including a plurality of storage capacitors each coupled to a corresponding one of the plurality of transistors; an interface structure on the second portion of the base structure; and a peripheral structure on the interface structure; wherein the interface structure is divided into a plurality of insulating films and the plurality of insulating films are arranged away from each other to have a plurality of voids between the second portion of the base structure and the peripheral structure.