DRAM Command Scheduling with Predictive Burst-Length Arbitration

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Solution Overview

Problem

The efficiency of dynamic random-access memory (DRAM) is affected by the Four Active Window (tFAW) constraint, leading to potential delays and discontinuities in data access.

Innovation Solution

A memory scheduling device and method that precomputes a predict burst length for main commands using a round-robin sequence and transmits secondary commands when the burst length is less than a threshold, ensuring all commands meet or exceed the threshold burst length to maintain efficient data access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the burst length is kept short to meet tFAW constraints, then memory access efficiency is improved, but memory utilization decreases

Engineering Contradiction:
Improvememory access efficiencyVSAvoidmemory utilization
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The system precomputes the predict burst length based on the round-robin sequence before actual memory access occurs. This preliminary calculation allows the scheduler to anticipate whether the burst length will meet the tFAW constraint and proactively adjust command selection accordingly, resolving the contradiction between short bursts for efficiency and sufficient burst length for utilization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically changes the burst length parameter by selecting different commands (main commands or secondary commands) based on the predicted burst length. When the predict burst length is insufficient, the system switches to secondary commands that can extend the burst length to meet the threshold, thereby adjusting the parameter to satisfy both efficiency and utilization requirements.

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If secondary commands are used to extend burst length, then memory utilization is improved, but command complexity increases

Engineering Contradiction:
Improvememory utilizationVSAvoidcommand scheduling complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The command queue is segmented into main commands and secondary commands with distinct roles. Main commands are processed normally, while secondary commands are reserved for extending burst length when necessary. This segmentation simplifies the scheduling logic by clearly defining when each command type should be used, reducing the overall complexity of command management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The scheduler acts as an intermediary between the command queue and the memory controller. It precomputes burst lengths, selects appropriate commands, and manages the transition between main and secondary commands. This intermediary role simplifies the system by centralizing the decision-making logic in one component rather than distributing complexity throughout the entire system.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12608134B2Memory scheduling device and memory scheduling method
Publication Date: 2026.04.21 REALTEK SEMICON CORP
  • US12608134B2 patent drawing
  • US12608134B2 patent drawing
  • US12608134B2 patent drawing

AI summary

A memory scheduling device includes a pre-processing storage, a selector, a current storage, and an arbiter. The pre-processing storage provides a plurality of main commands and a plurality of secondary commands. The selector selects the main commands and/or the secondary commands based on a selection signal. The current storage receives the main commands and/or the secondary commands transmitted from the selector. The arbiter precomputes a predict burst length corresponding to the main commands expected to be received by the current storage based on a round-robin sequence. If the predict burst length corresponding to the main commands is less than a threshold burst length, the arbiter transmits the selection signal to the selector, such that the pre-processing storage transmits a portion of main commands and at least one secondary command of the secondary commands to the current storage through the selector.