DRAM Error Correction Using Burst RMW to Cut Bandwidth Loss
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Solution Overview
Problem
Conventional error correction devices in DRAM systems require a long processing time for read-modify-write operations, leading to performance degradation and reduced DRAM bandwidth utilization, especially at higher data transfer speeds.
Innovation Solution
The implementation of a burst read and write error correction device utilizing a Reed-Solomon engine, memory controller, and computing unit to perform logic operations on data groups, reducing the number of commands needed for error correction by executing burst operations and storing modified data in a second memory before writing it back to DRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RMW operations are used for error correction, then data accuracy is maintained, but processing time increases and DRAM bandwidth utilization decreases
Solution Approach 1:
The patent segments the error correction process into two distinct phases: a read phase where data is read from DRAM without modification, and a write phase where corrected data is written back to DRAM. This segmentation eliminates the need for repeated read-modify-write cycles, thereby reducing processing time while maintaining data accuracy through the buffer's correction capability
Solution Approach 2:
The patent introduces a buffer as an intermediary component between the DRAM and the error correction logic. The buffer temporarily stores data and performs error correction independently, acting as a mediator that prevents the need for time-consuming RMW operations on the main memory, thus reducing processing time while preserving data integrity
2Reliability
If conventional RMW operations are used for error correction, then data errors are corrected, but DRAM bandwidth utilization is reduced
Solution Approach 1:
By segmenting error correction operations into separate read and write phases with buffered intermediate storage, the patent enables parallel processing of other data transactions during the buffer's correction time, thereby maintaining high DRAM bandwidth utilization while preserving error correction capability
Solution Approach 2:
The buffer performs error correction autonomously using its own dedicated logic and error correction codes, without requiring continuous DRAM access cycles. This self-service capability allows the DRAM to maintain high bandwidth utilization for other productive operations while the buffer independently corrects errors in its stored data
3Measurement precision
If multiple commands are sent for each byte modification, then precise error correction is achieved, but cycle count increases
Solution Approach 1:
The patent performs preliminary data reading and error detection in the buffer before the actual correction write operation. Error correction codes are calculated and corrections are prepared in advance during the read phase, allowing the write phase to simply apply pre-computed corrections, thereby achieving precise error correction with minimal cycle count
Solution Approach 2:
The patent maintains continuous useful action by overlapping the error correction computation with data transfer operations. While data is being transferred to the buffer, error correction codes are being computed, and while data is being corrected in the buffer, other data transactions continue with the DRAM, eliminating idle cycles and reducing overall correction time while maintaining precision
Data Source
AI summary
An error correction device is provided. When an error of a data group stored in a dynamic random access memory (DRAM) device is detected, a memory controller of the error correction device executes a burst read and write, burst write or burst read-modify-write (RMW) operations to the DRAM instead of the conventional single read-modify-write (RMW) operation, thereby reducing the occupied bandwidth of the DRAM.