DRAM Error Correction Circuit Using Parallel Byte Decoding
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Solution Overview
Problem
As semiconductor memory technologies advance and memory density increases, errors in Dynamic Random Access Memory (DRAM) become more prevalent, necessitating effective error correction mechanisms to maintain performance.
Innovation Solution
An error correction system is implemented in the memory system, which generates X first operation codes and Y second operation codes during read or write operations. This system includes M decoding units, each with a decoder, a first AND gate unit, a NOR gate unit, and N second AND gate units, configured to perform error detection and correction on multiple data divided into M bytes, each with N bits, optimizing error detection and correction speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction methods are used in high-density DRAM, then error detection and correction capability is maintained, but error detection and correction speeds decrease and hardware complexity increases
Solution Approach 1:
The patent divides the data into M bytes and processes each byte independently through separate decoding units. Each decoding unit handles a specific byte using dedicated logic circuits including decoders, AND gate units, and NOR gate units. This segmentation allows parallel processing of multiple bytes simultaneously, thereby maintaining high error correction capability while improving detection and correction speeds through concurrent operations.
Solution Approach 2:
The patent introduces a hierarchical error correction approach with two dimensions: byte-level error detection using second operation codes and bit-level error correction within each byte using first operation codes. This dual-dimensional structure enables the system to handle errors at multiple levels of granularity, improving overall error correction capability while maintaining efficient processing through the organized hierarchical architecture.
2Reliability
If more decoding units are added to handle multiple bytes, then error correction capability is improved, but hardware requirements and power consumption increase
Solution Approach 1:
The patent designs each decoding unit with a universal structure that can process any byte independently. The same types of components (decoder, first AND gate unit, NOR gate unit, and N second AND gate units) are reused across all M decoding units. This modular universal design allows the system to handle multiple bytes with identical hardware templates, improving error correction capability while controlling hardware complexity through component reuse and standardization.
Data Source
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AI summary
Embodiments of the disclosure provide an error correction system including: M decoding units, each configured to perform decoding on the X first operation codes and the Y second operation codes; here the decoding unit includes: a decoder, configured to receive the X first operation codes and output N first decoded signals, each of the N first decoded signals corresponding to a respective one bit of the N data; a first AND gate unit, configured to receive and perform a logical AND operation on Z selected operation codes; an NOR gate unit, configured to receive and perform a logical NOR operation on (Y-Z) unselected operation codes; and N second AND gate units, each having an input terminal connected to an output terminal of the first AND gate unit, an output terminal of the NOR gate unit and one of the first decoded signals, here at least one of error detection or error correction is performed on the memory system based on the output of the N second AND gate units.