DRAM Cache for Second-Type Memory With In-Line Directory Storage
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Solution Overview
Problem
Current computing systems face challenges in using DRAM as a cache for second type memory due to directory size limitations, resource consumption, and the need for additional bits in DRAM, which impact processor and memory design, and require significant engineering work.
Innovation Solution
Implementing a DRAM cache that uses spare bits for data compression and stores a cache directory and data in the same memory line, eliminating the need for additional directory bits and allowing direct mapping, thereby reducing resource consumption and design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional directory bits are added to DRAM to store cache directory information, then cache functionality is achieved, but device complexity and resource consumption increase
Solution Approach 1:
The patent merges the cache directory and data into a single memory line structure. The cache directory is stored in the upper bytes of the memory line while data is stored in the lower bytes, eliminating the need for separate directory bits. This combining approach achieves cache functionality without increasing device complexity.
Solution Approach 2:
The memory line structure is designed to serve multiple functions: it stores both cache directory information and actual data, and can be directly mapped to memory addresses. This multi-functional design eliminates the need for additional specialized components and reduces overall system complexity.
2Loss of energy
If spare bits in DRAM are used for data compression, then memory bus bandwidth consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the parameter of data representation by using compression algorithms to reduce the number of bits needed to store data. By compressing data before storing it in the DRAM cache, the system reduces memory bus bandwidth consumption. The compression is performed at the software level, so manufacturing precision requirements remain manageable.
3Productivity
If DRAM is configured as cache for second type memory, then bandwidth and capacity are maintained, but processor and memory design complexity increases
Solution Approach 1:
The patent segments the memory system into two distinct parts: a DRAM cache portion for high-speed access and a second type memory portion for high-capacity storage. This segmentation allows each component to be optimized for its specific function while maintaining overall system performance. The direct mapping approach simplifies the design by creating clear, non-overlapping address spaces.
Data Source
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AI summary
Various embodiments are provided for providing a dynamic random-access memory ("DRAM") cache as second type memory in a computing system by a processor. A selected amount of bytes in a memory line may be cleared using one or more spare bits of the DRAM, a data compression operation, or a combination thereof. A cache directory and data may be stored in the memory line. The DRAM cache is configured as a cache of a second type memory.