DRAM Cache Tag Updates for Non-Blocking Miss Handling
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Solution Overview
Problem
Existing DRAM cache systems face issues with increased latency and bandwidth consumption due to metadata access in hardware-based designs, and application interruptions in OS-managed systems, necessitating a method to quickly update tags without additional bandwidth and minimize application interruptions.
Innovation Solution
A DRAM cache system employing a front-end module for non-blocking miss processing through decoupled tag-data management, utilizing a translation lookaside buffer and page table entry to offload cache-fill commands to a back-end module, with additional bits in the PTE for tag management and a background eviction daemon for proactive eviction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware-based DRAM cache stores metadata in on-package DRAM, then non-blocking miss handling is achieved, but additional bandwidth consumption increases and effective cycle time increases
Solution Approach 1:
The patent segments the cache system into front-end module (handling tags and metadata) and back-end module (handling data), allowing independent optimization of each component and reducing the bandwidth burden on on-package DRAM
Solution Approach 2:
The patent extracts metadata management from the traditional hardware-based cache controller and relocates it to the front-end module, which can manage tags without requiring additional on-package DRAM bandwidth for metadata access
2Quantity of substance
If OS-managed DRAM cache implements coupled tag-data management, then bandwidth efficiency is improved, but application interruption occurs during cache fill
Solution Approach 1:
The patent implements dynamic tag management where tags can be updated independently of data availability, allowing the system to transition from static coupled management to dynamic decoupled management, thereby reducing application latency
Solution Approach 2:
The front-end module performs preliminary tag updates before data is fully available from the back-end module, allowing applications to resume execution without waiting for complete cache fill operations
3Reliability
If hardware-based DRAM cache accesses metadata in on-package DRAM, then cache functionality is achieved, but effective cycle time increases and performance degrades
Solution Approach 1:
The patent introduces a front-end module as an intermediary between the cache system and on-package DRAM, managing metadata access efficiently and reducing the cycle time impact of metadata operations
Data Source
AI summary
Disclosed are a DRAM cache system and an operating method thereof. The DRAM cache system includes a front-end module including a translation lookaside buffer (TLB) and a page table entry (PTE) and a back-end module, and the operating method includes checking, by the front-end module, the PTE when a TLB miss occurs in association with a memory request, calling, by the front-end module, a miss handler when a result of the checking the PTE is a tag miss, performing, by the front-end module, a tag update corresponding to the memory request through the miss handler, and offloading, by the front-end module, a cache-fill command to the back-end module.