3D DRAM Capacitor Structure With Supporting Layers for Cell Scaling
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) manufacturers face challenges in minimizing memory cell area due to reduced word line spacing, which affects the miniaturization and complexity of integrated circuits.
Innovation Solution
A semiconductor device with capacitors arranged along a plane perpendicular to the substrate surface, incorporating supporting layers to reinforce the structure and increase the length of capacitor electrodes, thereby reducing overall thickness and enhancing capacitor density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If word line spacing is reduced to minimize memory cell area, then memory cell area is reduced, but manufacturing precision and structural stability deteriorate
Solution Approach 1:
The patent transitions from planar capacitor arrangement to vertical three-dimensional arrangement. Capacitors are positioned along a vertical axis extending from the substrate surface, allowing memory cells to be stacked in multiple layers. This dimensional change enables continued area reduction while maintaining adequate spacing and manufacturing precision through vertical separation rather than horizontal compression.
2Quantity of substance
If capacitor electrodes are made longer to increase capacitor density, then capacitor density increases, but structural stability and electrode strength deteriorate
Solution Approach 1:
The extended capacitor electrode structure is divided into multiple segments separated by insulating layers. Each electrode segment is shorter and structurally stronger than a single continuous long electrode. The insulating layers provide mechanical support and electrical isolation, allowing the overall electrode length to be extended for increased density while maintaining the strength of individual segments.
Solution Approach 2:
Insulating layers are introduced as intermediary structures between electrode segments. These intermediary layers provide mechanical support to prevent electrode collapse and maintain structural integrity during manufacturing and operation. The insulating material acts as a mediator that enables longer overall electrode length while preserving the strength of individual electrode portions.
3Length of stationary object
If three-dimensional capacitor structure is implemented to reduce thickness, then device thickness is reduced, but device complexity increases
Solution Approach 1:
The patent employs universal manufacturing processes and materials that serve multiple functions. The same deposition and patterning techniques used for planar structures are adapted for vertical three-dimensional structures. Insulating layers simultaneously provide electrical isolation, mechanical support, and structural definition. This multi-functionality reduces the need for specialized complex processes while achieving thickness reduction.
Data Source
AI summary
A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.