Vertical DRAM Capacitor Contacts With Silicide Barrier Stack
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Solution Overview
Problem
The DRAM with vertical channel transistors faces issues of high contact resistance between the capacitor structures and active pillars, and contamination of the etching chamber during the etching of capacitor holes, which affect the performance and precision of the semiconductor structure.
Innovation Solution
The semiconductor structure incorporates capacitor contact structures with metal silicide layers, diffusion barrier layers, and metal layers, arranged between active pillars and capacitor structures, with the diffusion barrier layers' top surfaces set lower than the recesses to avoid contamination and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional capacitor contact structures are used to connect capacitor structures and active pillars, then electrical connection is established, but contact resistance remains high
Solution Approach 1:
The capacitor contact structure employs a composite material architecture consisting of a metal silicide layer (such as tungsten silicide or cobalt silicide) combined with a metal layer (such as tungsten, copper, or aluminum). This composite structure leverages the low resistivity of metals and the excellent adhesion and stability of metal silicides to the semiconductor substrate, thereby reducing contact resistance while improving current transmission rate and electrical reliability.
2Reliability
If capacitor holes are etched to establish electrical connection, then contact is formed, but etching chamber contamination occurs
Solution Approach 1:
A diffusion barrier layer (such as titanium nitride or tantalum nitride) is introduced as an intermediary between the metal silicide layer and the surrounding environment. This barrier layer serves multiple functions: it prevents contamination of the etching chamber during capacitor hole etching, blocks diffusion of metal atoms into the semiconductor substrate, and maintains the structural integrity of the contact structure. By positioning this intermediary layer strategically, the patent eliminates the harmful contamination effect while preserving the essential electrical connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces contact resistance, improves transmission rate, and maintains etching precision by preventing etching chamber contamination, enhancing the performance and reliability of the vertical channel transistor.
Implementation Method 1
the capacitor contact structures include metal silicide layers, diffusion barrier layers, and metal layers that are sequentially arranged in an extension direction of the plurality of active pillars, the metal silicide layers are in contact with the plurality of active pillars
Implementation Method 2
top surfaces of the diffusion barrier layers are lower than top surfaces of the first recesses
Data Source
AI summary
A semiconductor structure includes: a substrate, a plurality of active pillars, first recesses, first insulating layers; and capacitor contact structures; wherein the capacitor contact structures include metal silicide layers, diffusion barrier layers, and metal layers that are sequentially arranged in an extension direction of the plurality of active pillars, the metal silicide layers are in contact with the plurality of active pillars, and top surfaces of the diffusion barrier layers are lower than top surfaces of the first recesses.