DRAM Capacitor Dielectric Deposition for Uniform Thickness
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Solution Overview
Problem
Dynamic Random-Access Memory (DRAM) capacitors face issues with non-uniform dielectric layer thickness due to differences in space environment and reaction rates, leading to low breakdown voltage and high electric field leakage, affecting storage device performance.
Innovation Solution
A semiconductor structure manufacturing method involving a stack structure with alternately stacked sacrificial and support layers, forming capacitance holes, electrode layers, and dielectric layers to ensure uniform thickness and leakage current, where a first dielectric layer is pre-deposited to compensate for thickness differences before removing the sacrificial layer, resulting in improved electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the capacitor dielectric layer is deposited in a conventional manner, then the deposition process is simple and fast, but the inner capacitor dielectric layer has lower deposition rate than the outer layer, resulting in non-uniform thickness
Solution Approach 1:
A first dielectric layer is pre-deposited on the inner surface of the first electrode layer before removing the sacrificial layer. This preliminary action compensates for the slower deposition rate in the inner capacitance hole, ensuring that the second dielectric layer achieves uniform thickness across both inner and outer surfaces after the sacrificial layer is removed.
2Reliability
If the dielectric layer thickness is non-uniform, then the manufacturing process is simpler, but the breakdown voltage is low and electric field leakage is high
Solution Approach 1:
The first dielectric layer is deposited in advance on the inner electrode surface to compensate for the slower deposition rate that occurs in the confined space of the inner capacitance hole. This ensures that when the second dielectric layer is deposited after sacrificial layer removal, both inner and outer surfaces achieve uniform and sufficient thickness, thereby improving breakdown voltage and reducing electric field leakage.
3Manufacturing precision
If the inner capacitor dielectric layer is deposited with sufficient thickness, then the breakdown voltage improves, but the deposition rate is too slow due to insufficient reaction gas and slow removal of reaction products
Solution Approach 1:
The first dielectric layer is pre-deposited on the inner electrode surface before sacrificial layer removal. This allows the inner surface to accumulate sufficient dielectric thickness in advance when the deposition environment is more favorable, avoiding the need for prolonged deposition in the confined space after sacrificial layer removal, thereby maintaining higher overall deposition efficiency.
Solution Approach 2:
The dielectric layer formation is divided into two separate steps: first depositing the first dielectric layer on the inner surface, then removing the sacrificial layer and depositing the second dielectric layer. This segmentation allows optimization of deposition conditions for each step, ensuring sufficient thickness while managing deposition rate constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures uniform leakage current and enhanced electrical properties by adjusting the thickness of dielectric layers, addressing the non-uniformity issues and improving the performance of DRAM storage devices.
Implementation Method 1
forming a first dielectric layer on an inner surface of the first electrode layer
Implementation Method 2
forming a second dielectric layer on an inner surface of the first dielectric layer and an outer surface of the first electrode layer
Data Source
AI summary
A semiconductor structure manufacturing method includes: providing a substrate; forming, on the substrate, a stack structure including a sacrificial layer and a support layer which are alternately stacked on each other; forming a capacitance hole in the stack structure; forming a first electrode layer on a side wall and a bottom of each capacitance hole; forming a first dielectric layer on an inner surface of the first electrode layer; forming, on the stack structure, an opening from which the sacrificial layer is exposed, and removing the sacrificial layer through the opening; forming a second dielectric layer on an inner surface of the first dielectric layer and an outer surface of the first electrode layer; and forming a second electrode layer on an inner surface and an outer surface of the second dielectric layer.