DRAM Capacitor Electrode Structure for Capacity and Stability

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Solution Overview

Problem

The challenge of maintaining sufficient capacitor storage capacity while ensuring stability becomes difficult with the high depth-to-width ratio in DRAM capacitors due to the miniaturization and high integration demands in semiconductor technologies.

Innovation Solution

A semiconductor structure is designed with a pillar-shaped conductive structure and a cup-shaped conductive structure forming a lower electrode, accompanied by a dielectric layer and an upper electrode, which enhances storage capacity and stability by reducing interference and maintaining a high depth-to-width ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the height of DRAM capacitor is increased to achieve high depth-to-width ratio for high integration, then the storage capacity per unit area is improved, but the stability of capacitor structure deteriorates

Engineering Contradiction:
Improvestorage capacity per unit areaVSAvoidcapacitor structure stability
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

The lower electrode is segmented into two distinct parts: a pillar-shaped conductive structure at the bottom and a cup-shaped conductive structure at the top. This segmentation allows each part to fulfill specific functional requirements - the pillar provides structural support and vertical extension for high depth-to-width ratio, while the cup-shaped structure provides stability and supports the dielectric layer, thereby resolving the contradiction between height increase and structural stability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The lower electrode employs an asymmetric design where the pillar-shaped conductive structure has a smaller cross-sectional area than the cup-shaped conductive structure. This asymmetric configuration creates a stable base (cup-shaped) that supports the taller pillar structure, enabling the capacitor to achieve high depth-to-width ratio while maintaining structural stability through the wider top portion.

Inventive Principle:
Principle #4Asymmetry

2Area of stationary object

If miniaturization is pursued to reduce manufacturing process size, then integration density is improved, but the capacitor storage capacity deteriorates

Engineering Contradiction:
Improvemanufacturing process sizeVSAvoidcapacitor storage capacity
Core Design Contradiction:
Area of stationary objectVSQuantity of substance

Solution Approach 1:

The capacitor structure transitions from a planar two-dimensional layout to a three-dimensional vertical structure with high depth-to-width ratio. The pillar-shaped and cup-shaped conductive structures extend vertically, allowing the capacitor to achieve sufficient storage capacity within a reduced footprint area, thereby resolving the contradiction between miniaturization and storage capacity maintenance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12396157B2Preparation method for semiconductor structure, semiconductor structure and semiconductor memory
Publication Date: 2025.08.19 CHANGXIN MEMORY TECH INC
  • US12396157B2 patent drawing
  • US12396157B2 patent drawing
  • US12396157B2 patent drawing

AI summary

A preparation method for a semiconductor structure includes the following operations. A bit line structure, active pillars, and a word line structure are formed in turn on a substrate. Bottom ends of the active pillars are connected to the bit line structure, and the active pillars are connected with the word line structure. A pillar-shaped conductive structure is formed on the active pillars, and a cup-shaped conductive structure is formed on the pillar-shaped conductive structure. There is an electrode gap between the pillar-shaped conductive structure and the cup-shaped conductive structure, and the pillar-shaped conductive structure and the cup-shaped conductive structure form a lower electrode. A dielectric layer is formed on a surface of the lower electrode. An upper electrode is formed on a surface of the dielectric layer. The upper electrode fills the electrode gap.