DRAM Capacitor Hole Segmentation to Prevent Etch Loading
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Solution Overview
Problem
The etch loading effect during the fabrication of capacitor holes in the core area of dynamic random access memory (DRAM) leads to reliability issues due to inconsistent etching depths and sizes, affecting the performance of capacitor structures.
Innovation Solution
The formation of capacitor holes is divided into first and second regions, with specific electrode and dielectric layers formed in both regions, followed by selective removal of layers in the second region to ensure uniformity and consistency, thereby avoiding under-etching and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If capacitor holes are formed in the core area using conventional etching methods, then the fabrication process can be completed, but the etch loading effect causes inconsistent etching depths and sizes, reducing reliability
Solution Approach 1:
The patent divides the core area into multiple etching regions with different etching conditions. Specifically, different etching parameters (such as etching depth, etching rate, or etching chemistry) are applied to different spatial zones within the core area to compensate for the etch loading effect. This segmentation allows each region to achieve consistent capacitor hole dimensions despite varying local etching loads, thereby improving both manufacturing precision and reliability.
2Manufacturing precision
If the etch loading effect is addressed by adjusting etching parameters, then etching uniformity can be improved, but the fabrication process complexity increases
Solution Approach 1:
The patent implements local quality by assigning different etching characteristics to different regions of the core area. Each region is optimized with specific etching parameters tailored to its local conditions (such as proximity to edges, density of capacitor holes, or underlying structure). This localized approach achieves uniform capacitor hole dimensions across the entire core area while avoiding the need for completely separate fabrication processes, thus balancing precision improvement with process complexity management.
Data Source
Figure 1~2A
Figure 2B~2C
Figure 2D~2E
AI summary
A semiconductor structure and a fabrication method thereof, a memory and a memory system are provided. The method includes: forming a plurality of capacitor holes penetrating through a first stack layer comprising a first region and a second region where the capacitor holes are located; forming a first electrode layer on inner walls of the capacitor holes; forming a dielectric layer in the first region and the second region; forming a second electrode layer on a side of the dielectric layer; removing the second electrode layer on the first stack layer in the second region; and forming a contact structure penetrating through the first stack layer in the second region. The method can prevent an etch loading effect from occurring in the first region during formation of the capacitor holes, which is favorable to form capacitor structures with a uniform size, thus improving reliability of the capacitor structures.