DRAM Capacitor Array Filling Structure to Block Parasitic Capacitance
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Solution Overview
Problem
In the manufacturing of DRAM capacitor array structures, the diffusion of the dielectric layer into gaps in the bottom supporting layer forms parasitic capacitance, leading to performance delays.
Innovation Solution
A method involving the formation of a filling layer with varying thicknesses in the array and peripheral regions to fill gaps in the bottom supporting layer, preventing dielectric layer diffusion and ensuring the stability of the capacitor array structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the dielectric layer is deposited at high temperature, then the dielectric layer can be formed with good coverage, but the dielectric layer diffuses into the gap of the bottom supporting layer forming parasitic capacitance
Solution Approach 1:
The filling layer is formed in advance before the dielectric layer deposition. This preliminary action prevents the dielectric layer from diffusing into the gap during subsequent high-temperature deposition, thereby avoiding parasitic capacitance formation while maintaining good coverage quality.
Solution Approach 2:
The filling layer acts as an intermediary barrier between the gap in the bottom supporting layer and the dielectric layer. It prevents direct contact and diffusion between the dielectric layer and the gap, eliminating the harmful parasitic capacitance effect while allowing the dielectric layer to be deposited with good coverage.
2Ease of manufacture
If the filling layer thickness is uniform across the substrate, then the manufacturing process is simpler, but the conductive structure at the peripheral region cannot be protected
Solution Approach 1:
The filling layer is designed with different thicknesses in different regions: a first thickness in the array region and a second (greater) thickness in the peripheral region. This local quality differentiation protects the conductive structure at the peripheral region while maintaining process feasibility through selective thickness control.
Solution Approach 2:
The filling layer exhibits asymmetric thickness distribution across the substrate, with the peripheral region having a greater thickness than the array region. This asymmetric design provides enhanced protection to the conductive structure at the periphery without compromising the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance, alleviates delay effects, and enhances the performance of DRAM by preventing dielectric layer diffusion and protecting the conductive structure at the peripheral region.
Implementation Method 1
forming a filling layer filling the gap and covering the capacitor contact and a surface of the bottom supporting layer... preventing dielectric layer diffusion
Data Source
AI summary
A method for forming a capacitor array structure includes the following steps: providing a substrate, a capacitor contact being exposed on a surface of the substrate, and the substrate including an array region and a peripheral region; forming a bottom supporting layer covering the substrate and the capacitor contact, the bottom supporting layer having a gap therein; forming a filling layer filling the gap and covering the capacitor contact and the surface of the bottom supporting layer, a thickness of the filling layer located at the peripheral region being larger than that of the filling layer located at the array region; forming supporting layers and sacrificial layers alternately stacked in a direction perpendicular to the substrate; forming a capacitor hole; sequentially forming a lower electrode layer on an inner wall of the capacitor hole.