DRAM Capacitor Hole Layout for Higher Capacitance Without Collapse
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Solution Overview
Problem
The integration of capacitors in semiconductor memory devices is limited by their vertical design, which increases capacitance per unit area but makes them prone to collapse due to increased height.
Innovation Solution
The formation of two U-shaped lower electrode layers connected to a single electrical contact portion through two or more capacitor holes, allowing for reduced key dimensions and size flexibility without photolithography constraints, thereby enhancing integration and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitors are designed in a vertical shape to increase height, then capacitance value per unit area is improved, but capacitors become prone to collapse
Solution Approach 1:
The invention divides a single capacitor structure into multiple segmented capacitor holes (e.g., two or more holes) formed on the same electrical contact portion. Each hole forms a separate capacitor structure with the lower electrode layer, allowing the total capacitance to be distributed across multiple smaller units rather than relying on a single tall structure, thereby improving reliability while maintaining integration.
Solution Approach 2:
The invention transitions from a single vertical dimension approach to a multi-dimensional configuration by forming multiple capacitor holes in the same planar area. This allows capacitance to be increased through spatial distribution in the horizontal plane while reducing the vertical height requirement of individual capacitor structures, thus preventing collapse.
2Manufacturing precision
If traditional photolithography and etching processes are used to form capacitor holes, then manufacturing precision is achieved, but size limitations and high costs are imposed
Solution Approach 1:
The invention replaces the traditional photolithography and etching process with an ion implantation-based method to form the mask pattern. By using ion implantation to create doped regions with different etch rates in the mask layer, the need for photolithography is eliminated, allowing for greater size flexibility and reduced costs while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method increases capacitance per unit area while reducing the height of capacitor holes, preventing collapse and improving integration without the size limitations and high costs associated with traditional photolithography and etching processes.
Implementation Method 1
forming at least two first portions or two second portions with different doping densities in the mask layer through doping process
Implementation Method 2
selectively removing the two first portions or two second portions
Data Source
Figure 1~2
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Figure 5~6A
AI summary
Disclosed are capacitors (1211, 1212), a forming method therefor, and a DRAM unit. The forming method for the capacitors (1211, 1212) comprises: providing a substrate (100), wherein an electrical contact part (101) is formed in the substrate (100); forming a dielectric layer (110) on the surface of the substrate (100), the dielectric layer (110) comprising: support layers (102, 104, 106) and sacrificial layers (103, 105) that are alternatingly stacked; forming at least two capacitor holes (601) that penetrate the sacrificial layers (103, 105) and the support layers (102, 104, 106) and expose the same electrical contact part (101); forming a lower electrode layer (701) that covers the inner wall of the capacitor holes (601), the lower electrode layer (701) being connected to the electrical contact part (101); removing the sacrificial layers (103, 105); successively forming a capacitor dielectric layer (1101) and an upper electrode layer (1102) at inner and outer surfaces of the lower electrode layer (701) and at surfaces of the support layers (102, 104, 106). The described method may improve the capacitance value per unit area of the capacitors (1211, 1212).