DRAM Capacitor Structure With Multi-Level Lateral Electrode Support
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to instability in capacitor array regions, causing potential collapse or overturning of bottom electrodes, which affects the performance reliability and capacitance value of DRAM structures.
Innovation Solution
A method involving the formation of a stacked structure with alternating supporting and sacrificial layers, followed by selective etching and removal processes to create a capacitor structure with multiple lateral supporting layers, enhancing the stability and height of the electrode while reducing its thickness, thereby improving lateral stability and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of the bottom electrode is increased to maintain capacitance value during miniaturization, then the capacitance value is maintained, but the aspect ratio increases and lateral stability deteriorates
Solution Approach 1:
The supporting layer is divided into multiple segments (first supporting layer, second supporting layer, third supporting layer) stacked vertically. Each segment provides localized support to the bottom electrode, distributing the mechanical load and improving lateral stability without requiring a single tall supporting structure that would increase aspect ratio.
Solution Approach 2:
Instead of increasing height in the vertical dimension to maintain capacitance, the solution introduces lateral support through multiple stacked supporting layers at different heights. This transforms the problem from a vertical height issue to a multi-level lateral support structure, reducing aspect ratio while maintaining both capacitance and stability.
2Length of stationary object
If the thickness of the bottom electrode is decreased to reduce aspect ratio, then the aspect ratio is reduced, but the lateral stability and risk of overturning increase
Solution Approach 1:
The multiple supporting layers are formed beforehand before the bottom electrode is fully processed. The first supporting layer is formed initially, then the bottom electrode, followed by additional supporting layers stacked above it. This preliminary arrangement of support structures ensures lateral stability is established before the electrode is subjected to subsequent processing steps that could cause overturning.
Solution Approach 2:
The supporting structure uses composite material architecture with multiple layers of different materials (first supporting layer, second supporting layer, third supporting layer) stacked vertically. Each layer can be optimized for specific mechanical properties, providing comprehensive lateral support to the thin bottom electrode through combined structural strength.
3Stability of the object's composition
If a single lateral supporting layer is added to improve stability, then lateral stability is improved, but the height limit is reached and capacitance value is constrained
Solution Approach 1:
The single lateral supporting layer is segmented into multiple vertical layers (first, second, and third supporting layers) stacked at different heights. Each segment contributes to lateral stability independently, allowing the bottom electrode to be supported at multiple levels without requiring any single layer to be excessively tall, thus avoiding capacitance constraints.
Solution Approach 2:
The supporting structure is made dynamic through the buffer layer that can be selectively removed in etching windows. This allows the supporting layers to adapt their configuration - providing maximum support where needed while allowing the bottom electrode to protrude in specific regions for electrical connection, optimizing both stability and electrical performance.
Data Source
AI summary
A method for forming a semiconductor structure and a semiconductor structure are provided. The method includes: a stacked structure is formed on a surface of a substrate, the stacked structure including supporting layers and sacrificial layers which are alternately stacked; a buffer layer is formed on a surface of the stacked structure facing away from the substrate; capacitor holes penetrating through the stacked structure and the buffer layer and exposing capacitor contacts are formed; a first electrode layer covering inner walls of the capacitor holes is formed; an etching window penetrating through the buffer layer is formed; part of the supporting layers and all of the sacrificial layers in the stacked structure are removed along the etching window; the buffer layer is removed; and a dielectric layer and a second electrode layer are formed to form a capacitor.