Multilayer DRAM Capacitor Dielectric for Low Leakage
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Solution Overview
Problem
The increasing complexity in manufacturing and integration of dynamic random access memories (DRAMs) leads to deficiencies and a need for improved structure and manufacturing processes to enhance performance and packing densities.
Innovation Solution
A memory device with a multilayered capacitor dielectric structure, comprising different metal oxide layers such as ZrO2, Al2O3, and ZrO2 doped with dopants like Hf, Ta, La, Gd, Y, Sc, Ga, and lanthanide elements, formed using atomic layer deposition (ALD) processes, to reduce current leakage while maintaining capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dimensions of DRAM memory cells are continuously shrunk to increase packing densities, then the memory storage capacity is improved, but the manufacturing complexity and integration difficulty increase
Solution Approach 1:
The capacitor dielectric is segmented into multiple layers (first dielectric layer, second dielectric layer, third dielectric layer) with each layer having different material compositions and functions. This segmentation allows optimization of each layer's properties independently, enabling high capacitance in a compact structure that supports continued miniaturization without proportionally increasing manufacturing complexity
Solution Approach 2:
The patent employs composite dielectric materials including metal oxides (such as HfO2, Al2O3, SiO2) and nitrides (such as TiN, TaN) in different layers. These composite materials provide different functional properties (high-k dielectric constant, barrier properties, interface quality) that collectively achieve high capacitance in reduced space, enabling increased storage capacity while managing manufacturing complexity through specialized material functions
2Reliability
If a multilayered capacitor dielectric structure with different metal oxide layers is implemented, then current leakage is reduced and capacitance is maintained, but the manufacturing process complexity increases
Solution Approach 1:
Different dielectric layers are assigned specific local functions: the first dielectric layer (e.g., HfO2) provides high-k capacitance, the second dielectric layer (e.g., Al2O3) provides intermediate properties and interface quality, and the third dielectric layer (e.g., SiO2) provides barrier properties and stability. This local quality differentiation reduces current leakage through optimized interface and barrier properties while maintaining overall capacitance
Solution Approach 2:
The middle dielectric layer acts as an intermediary between the top and bottom dielectric layers, providing interface quality improvement and stress management. This intermediary layer prevents direct contact between potentially incompatible materials, reducing leakage paths while maintaining the functional properties of adjacent layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multilayered capacitor dielectric structure effectively reduces current leakage and maintains acceptable capacitance, thereby improving the overall performance of the memory device.
Implementation Method 1
formed using atomic layer deposition (ALD) processes
Data Source
AI summary
A memory device includes a semiconductor substrate having an active region, and a word line extending across the active region. The memory device also includes a first source/drain region and a second source/drain region disposed in the active region and at opposite sides of the word line, a bit line disposed over and electrically connected to the first source/drain region, and a capacitor disposed over and electrically connected to the second source/drain region. The capacitor includes a bottom electrode, a top electrode, and a capacitor dielectric structure disposed between them. The capacitor dielectric structure includes a first metal oxide layer, a second metal oxide layer disposed over the first metal oxide layer, and a third metal oxide layer disposed over the second metal oxide layer. The first, the second and the third metal oxide layer include materials that are different from each other.