DRAM Capacitor Electrode Structure for Low-Resistance Pad Contact
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Solution Overview
Problem
The current manufacturing process for dynamic random access memory (DRAM) capacitors faces issues with over-etching during the formation of the lower electrode, leading to damage of pads and reduced contact area due to the small width of the bottom portion of the formed hole, resulting in increased contact resistance.
Innovation Solution
A capacitor structure with a first electrode having a large width and a first support layer made of SiC or SiCO, surrounded by a second support layer, is formed using controlled oxidation and wet etching processes to ensure a large contact area and protect the underlying conductive device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a wet etching process is used to remove dielectric layers, then the etching process can effectively remove the first and second dielectric layers, but the bottom support layer is very likely to be removed due to over-etching, causing the pads to be damaged
Solution Approach 1:
The patent introduces a third dielectric layer as an intermediary protective layer between the bottom support layer and the etching process. This third dielectric layer is selectively removed after serving its protective function, allowing precise control of the etching process while preventing over-etching damage to the bottom support layer and pads
Solution Approach 2:
The patent applies a protective coating on the bottom support layer before the wet etching process. This preliminary protective action prevents over-etching damage during the removal of dielectric layers, ensuring the pads are not damaged while still achieving effective etching of the target layers
2Length of moving object
If the total thickness of support layers and dielectric layers is increased to accommodate a tall lower electrode, then the contact area between the lower electrode and pad is reduced, leading to increased contact resistance
Solution Approach 1:
The patent changes the geometry of the lower electrode from a simple vertical structure to one with an expanded bottom portion that spreads laterally. This dimensional change increases the contact area with the pad in the horizontal plane while maintaining the required electrode height, thereby reducing contact resistance
Solution Approach 2:
The patent creates an asymmetric lower electrode structure where the bottom portion has a different (larger) width than the upper portion. This asymmetric design allows the electrode to have sufficient height for capacitance while the wider base provides increased contact area with the pad, reducing contact resistance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a low contact resistance between the capacitor and the conductive device, while preventing damage to the conductive device during etching, thereby enhancing the capacitor's electrical connection.
Implementation Method 1
controlled oxidation and wet etching processes
Data Source
AI summary
Disclosed are a capacitor structure and a manufacturing method thereof. The capacitor structure includes a substrate, a first electrode, a first support layer, a second support layer, a capacitor dielectric layer and a second electrode. The substrate has a conductive device. The first electrode includes a first portion and a second portion connected to the first portion. The first portion is disposed on the conductive device, and the width of the first portion is greater than the width of the second portion. The first support layer is disposed on the substrate and surrounds the first portion of the first electrode. The second support layer is disposed above the first support layer and surrounds the second portion of the first electrode. The capacitor dielectric layer is disposed on the surface of the first electrode, the surface of the first support layer and the surface of the second support layer.