DRAM Capacitor Structure With Selective Fill Layer Etching

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Solution Overview

Problem

The current semiconductor fabrication process often results in short circuits between upper and lower electrodes due to over-etching and weak adhesion of high dielectric constant materials, leading to performance issues and low fabrication acceptance rates in dynamic random access memory (DRAM) devices.

Innovation Solution

A semiconductor structure and method involving the formation of a substrate with capacitive contacts and conductive contact pads, a filling layer between pads, and a stacked structure with supporting layers, where the etching selection ratio between the filling layer and supporting layers is greater than a preset value, preventing over-etching and short circuits by ensuring proper adhesion and selective etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If over-etching is performed to form through holes in the substrate, then the capacitance column structure can be formed, but the dielectric layer cannot be completely adhered onto the upper and lower electrodes, causing short circuit between electrodes

Engineering Contradiction:
Improvethrough hole formation precisionVSAvoidelectrode adhesion reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a protective film on the lower electrode before etching the through hole. This protective film prevents the etching solution from directly contacting and damaging the dielectric layer adhesion at the electrode interface, thereby ensuring reliable adhesion while still allowing through hole formation. The protective film is removed after etching, leaving the electrode-adhesion interface intact.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a protective film as an intermediary layer between the etching solution and the dielectric layer during through hole formation. This intermediary layer allows the etching process to proceed while protecting the critical electrode-adhesion interface from damage, thus resolving the contradiction between achieving through hole penetration and maintaining adhesion reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If the dielectric layer with high dielectric constant is used to form capacitance column, then the storage capacity is improved, but the adhesion property becomes weaker than electrically conductive materials, causing direct contact between upper and lower electrodes

Engineering Contradiction:
Improvecapacitance storage capacityVSAvoiddielectric layer adhesion
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a protective film on the lower electrode before depositing the dielectric layer. This protective film serves as an adhesion promoter that enhances the bonding between the dielectric layer and the electrode, ensuring that the high dielectric constant material maintains both its capacitive function and adequate adhesion strength.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The protective film acts as an intermediary layer between the electrically conductive lower electrode and the dielectric layer with high dielectric constant. This intermediary layer improves the interfacial adhesion properties, allowing the dielectric layer to maintain both its high capacitance storage capacity and sufficient mechanical adhesion to prevent short circuits.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If through holes are formed in the substrate, then the capacitance column structure can be completed, but the upper and lower electrodes directly contact each other, causing short circuit and memory failure

Engineering Contradiction:
Improvecapacitance column formationVSAvoidshort circuit prevention
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a protective film on the lower electrode before etching the through hole. This protective film prevents direct contact between the etching solution and the electrode interface, maintaining adhesion integrity throughout the through hole formation process and preventing short circuits between upper and lower electrodes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The protective film serves as an intermediary layer during the through hole etching process, allowing the etching to proceed while preventing direct contact between the upper and lower electrodes. This intermediary protection ensures that the capacitance column structure can be formed without creating short circuits, thereby improving both manufacturability and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively prevents short circuits, enhances the electrical properties, and increases the fabrication acceptance rate of DRAM devices by maintaining the integrity of the capacitance column structure without altering its dimensions.

Implementation Method 1

an etching selection ratio between the filling layer and the supporting layer in contact therewith is greater than a preset value

Methodology Applied
Scientific EffectEtching selection ratio:

Data Source

PatentUS11869931B2Semiconductor structure and method of forming the same
Publication Date: 2024.01.09 CHANGXIN MEMORY TECH INC
  • US11869931B2 patent drawing
  • US11869931B2 patent drawing
  • US11869931B2 patent drawing

AI summary

The present application relates to semiconductor structure and forming method comprising: forming substrate, wherein plurality of capacitive contacts are provided in the substrate, plurality of electrically conductive contact pads are provided at surface of the substrate to be correspondingly connected to plurality of capacitive contacts on one-to-one basis, and a space is present between every two adjacent electrically conductive contact pads; forming filling layer that is fully filled in the space; forming stacked structure at the filling layer and surface of the electrically conductive contact pads, wherein the stacked structure includes plurality of supporting layers stacked one-on-another along direction perpendicular to the substrate, the filling layer is in contact with the supporting layer disposed at bottom of the stacked structure, and etching selection ratio between the filling layer and the supporting layer in contact therewith is greater than preset value; and etching the stacked structure to form capacitance hole.