Integrated circuit device and method of manufacturing the same
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing integration density of integrated circuit devices, such as DRAM, has led to reduced capacitor areas, necessitating a structure that enhances capacitance while maintaining desired electrical characteristics and overcoming spatial limitations.
Innovation Solution
The integration of a stacked plate structure in the capacitor of DRAM, where a middle layer of metal silicide or metal silicon nitride is inserted between a doped silicon germanium layer and a tungsten plate layer, to improve electrical characteristics and product reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the integration density of DRAM is increased, then the area of unit cells is reduced, but the capacitor area is further reduced making it difficult to maintain desired capacitance
Solution Approach 1:
The patent transitions from a conventional planar capacitor structure to a stacked plate structure that extends in the vertical dimension. Multiple plate layers (first plate layer, second plate layer, third plate layer) are stacked vertically with dielectric layers between them, effectively utilizing the third dimension to increase capacitance without occupying additional horizontal area. This dimensional change allows the capacitor to maintain required capacitance values despite the reduced unit cell area caused by higher integration density.
2Ease of manufacture
If a doped silicon germanium layer and tungsten plate layer are directly contacted, then the manufacturing process is simplified, but interfacial resistance increases and electrical characteristics deteriorate
Solution Approach 1:
The patent introduces a middle layer composed of metal silicide or metal silicon nitride between the doped silicon germanium layer and the tungsten plate layer. This intermediary layer serves as a buffer that reduces interfacial resistance and improves electrical characteristics at the interface. The middle layer acts as a mediator that facilitates better electrical contact and prevents direct contact between the silicon germanium and tungsten layers, thereby resolving the electrical characteristic deterioration issue while maintaining manufacturing feasibility.
3Ease of manufacture
If hydrogen penetration occurs in the capacitor structure, then the manufacturing process is straightforward, but defects are generated reducing product reliability
Solution Approach 1:
The middle layer of metal silicide or metal silicon nitride serves as a barrier layer that prevents hydrogen penetration into the capacitor structure. This intermediary layer blocks hydrogen from reaching sensitive interfaces and causing defects, thereby improving product reliability. The hydrogen barrier function is achieved without significantly complicating the manufacturing process, as the middle layer can be formed using standard deposition techniques already employed in DRAM fabrication.
4Area of stationary object
If the capacitor structure is miniaturized to increase integration, then the area is reduced, but the capacitance maintenance becomes difficult
Solution Approach 1:
The stacked plate structure utilizes the vertical dimension to compensate for the reduced horizontal area. By stacking multiple plate layers vertically with dielectric layers between them, the effective capacitance-generating volume is increased without requiring additional horizontal space. This allows the capacitor to maintain the required capacitance value even when the overall capacitor footprint is miniaturized to accommodate higher integration densities.
Solution Approach 2:
The patent employs a composite structure consisting of multiple materials: doped silicon germanium, metal silicide, metal silicon nitride, tungsten, and various dielectric materials. This composite construction allows optimization of each layer's properties to contribute to the overall capacitance. The combination of different materials with complementary properties enables the miniaturized capacitor to achieve and maintain the required capacitance through synergistic effects of the composite structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively enhances capacitance and maintains desired electrical characteristics, while also improving product reliability by reducing interfacial resistance and hydrogen penetration, which can cause defects in capacitor structures.
Implementation Method 1
The proposed solution effectively enhances capacitance and maintains desired electrical characteristics, while also improving product reliability by reducing interfacial resistance
Implementation Method 2
The proposed solution effectively enhances capacitance and maintains desired electrical characteristics, while also improving product reliability by reducing interfacial resistance and hydrogen penetration
Data Source
AI summary
Provided is an integrated circuit device and method of manufacturing same, the integrated circuit device including: a substrate including a memory cell area and a peripheral circuit area around the memory cell area; a cell transistor in the memory cell area; a peripheral circuit transistor in the peripheral circuit area; a capacitor structure including a lower electrode on the cell transistor, a dielectric film on a surface of the lower electrode, and an upper electrode on the dielectric film; a stacked plate structure covering the capacitor structure; and an interlayer insulating film covering the stacked plate structure in the memory cell area and covering the peripheral circuit transistor in the peripheral circuit area, wherein the stacked plate structure includes: a first plate layer including doped silicon germanium (SiGe); a middle layer conformally covering the first plate layer and including a metal silicide (MxSiy) including a metal (M); and a second plate layer conformally covering the middle layer and including the metal (M) of the metal silicide.